JAJSEW3C may   2017  – january 2022 AWR1443

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 機能ブロック図
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
    3. 7.3 Pin Multiplexing
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1  Power Supply Sequencing and Reset Timing
      2. 8.9.2  Synchronized Frame Triggering
      3. 8.9.3  Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
        2. 8.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. 8.9.4.2.1 SPI Timing Conditions
          2. 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 8.9.4.3 SPI Peripheral Mode I/O Timings
          1. 8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5  LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6  General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7  Controller Area Network Interface (DCAN)
        1. 8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 8.9.8  Serial Communication Interface (SCI)
        1. 8.9.8.1 SCI Timing Requirements
      9. 8.9.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.9.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 8.9.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.10.1 QSPI Timing Conditions
        2. 8.9.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 8.9.10.3 QSPI Switching Characteristics
      11. 8.9.11 JTAG Interface
        1. 8.9.11.1 JTAG Timing Conditions
        2. 8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Interfaces
    4. 9.4 Subsystems
      1. 9.4.1 RF and Analog Subsystem
        1. 9.4.1.1 Clock Subsystem
        2. 9.4.1.2 Transmit Subsystem
        3. 9.4.1.3 Receive Subsystem
        4. 9.4.1.4 Radio Processor Subsystem
      2. 9.4.2 Main (Control) System
      3. 9.4.3 Host Interface
    5. 9.5 Accelerators and Coprocessors
    6. 9.6 Other Subsystems
      1. 9.6.1 ADC Channels (Service) for User Application
        1. 9.6.1.1 GP-ADC Parameter
    7. 9.7 Boot Modes
      1. 9.7.1 Flashing Mode
      2. 9.7.2 Functional Mode
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-Range Radar
    3. 10.3 Blind Spot Detector and Ultrasonic Upgrades
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

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発注情報
8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
NO.PARAMETERMINTYPMAXUNIT
1tc(SPC)MCycle time, SPICLK(4)25256tc(VCLK)ns
2(4)tw(SPCH)MPulse duration, SPICLK high (clock polarity = 0)0.5tc(SPC)M – 40.5tc(SPC)M + 4ns
tw(SPCL)MPulse duration, SPICLK low (clock polarity = 1)0.5tc(SPC)M – 40.5tc(SPC)M + 4
3(4)tw(SPCL)MPulse duration, SPICLK low (clock polarity = 0)0.5tc(SPC)M – 40.5tc(SPC)M + 4ns
tw(SPCH)MPulse duration, SPICLK high (clock polarity = 1)0.5tc(SPC)M – 40.5tc(SPC)M + 4
4(4)td(SPCH-SIMO)MDelay time, SPISIMO valid before SPICLK low, (clock polarity = 0)0.5tc(SPC)M – 3ns
td(SPCL-SIMO)MDelay time, SPISIMO valid before SPICLK high, (clock polarity = 1)0.5tc(SPC)M – 3
5(4)tv(SPCL-SIMO)MValid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)0.5tc(SPC)M – 10.5ns
tv(SPCH-SIMO)MValid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)0.5tc(SPC)M – 10.5
6(5)tC2TDELAYSetup time CS active until SPICLK high
(clock polarity = 0)		CSHOLD = 00.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 70.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5ns
CSHOLD = 10.5*tc(SPC)M + (C2TDELAY + 2)*tc(VCLK) – 70.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5
Setup time CS active until SPICLK low
(clock polarity = 1)		CSHOLD = 00.5*tc(SPC)M + (C2TDELAY+2)*tc(VCLK) – 70.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) + 7.5
CSHOLD = 10.5*tc(SPC)M + (C2TDELAY+3)*tc(VCLK) – 70.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) + 7.5
7(5)tT2CDELAYHold time, SPICLK low until CS inactive (clock polarity = 0)(T2CDELAY + 1) *tc(VCLK) – 7.5(T2CDELAY + 1) *tc(VCLK) + 7ns
Hold time, SPICLK high until CS inactive (clock polarity = 1)(T2CDELAY + 1) *tc(VCLK) – 7.5(T2CDELAY + 1) *tc(VCLK) + 7
8(4)tsu(SOMI-SPCL)MSetup time, SPISOMI before SPICLK low
(clock polarity = 0)		5ns
tsu(SOMI-SPCH)MSetup time, SPISOMI before SPICLK high
(clock polarity = 1)		5
9(4)th(SPCL-SOMI)MHold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)		3ns
th(SPCH-SOMI)MHold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)		3
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
GUID-6A6051CA-597B-42FA-BA69-77A213936CC3-low.gifFigure 8-7 SPI Controller Mode External Timing (CLOCK PHASE = 1)
GUID-0D966465-F3AA-4189-B6B9-BD329F855EEC-low.gifFigure 8-8 SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)