JAJSSO7 January 2024 AWR2544
ADVANCE INFORMATION
The device clock subsystem generates 76 to 81 GHz from an input reference of 50-MHz crystal. It has a built-in oscillator circuit followed by an Analog PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an x4 multiplier to create the required frequency in the 76 to 81-GHz spectrum. The RF synthesizer output can be modulated by the timing engine block to create the required waveforms for effective sensor operation or it can input a fixed signal of 1 GHz directly from APLL.
The Analog PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the quality of the generated clock.
Figure 8-2 describes the clock subsystem.