SWRS318 November   2024 AWR2944P

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram - AWR2944P
    2. 6.2 Pin Diagram - AWR2E44P
    3. 6.3 Pin Attributes
    4. 6.4 Signal Descriptions - Digital
    5. 6.5 Signal Descriptions - Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1  QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-4217F622-1EF7-45F6-B855-64CF2ED24728/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-64 #GUID-35EA1079-DDD6-4DC7-839D-D2FFA528448C/T4362547-65
      2. 7.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-236 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-237 #GUID-BF7326FD-4582-4010-B4F1-73F1B0C09FC2/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-244 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-245 #GUID-E6A0140B-9416-425D-8E79-C66C78DF3527/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-70 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-71 #GUID-E2D86041-CEF3-4EEB-A74A-C17A9547F543/T4362547-73
      3. 7.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1 RGMII Timing Conditions
          1. 7.12.3.1.1  RGMII Transmit Clock Switching Characteristics
          2. 7.12.3.1.2  RGMII Transmit Data and Control Switching Characteristics
          3. 7.12.3.1.3  RGMII Receive Clock Timing Requirements
          4. 7.12.3.1.4  RGMII Receive Data and Control Timing Requirements
          5. 7.12.3.1.5  RMII Transmit Clock Switching Characteristics
          6. 7.12.3.1.6  RMII Transmit Data and Control Switching Characteristics
          7. 7.12.3.1.7  RMII Receive Clock Timing Requirements
          8. 7.12.3.1.8  RMII Receive Data and Control Timing Requirements
          9. 7.12.3.1.9  MII Transmit Switching Characteristics
          10. 7.12.3.1.10 MII Receive Timing Requirements
          11. 7.12.3.1.11 MII Transmit Clock Timing Requirements
          12. 7.12.3.1.12 MDIO Interface Timings
      4. 7.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5  UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-70BFADF8-F963-4E61-84ED-23FDE518F1A0/T4362547-185
      7. 7.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 7.12.8  CSI2 Receiver Peripheral
        1. 7.12.8.1 CSI2 Switching Characteristics
      9. 7.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 7.12.10 General-Purpose Input/Output
        1. 7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-45 #GUID-D645D302-151E-4A83-B5A0-36D93909E00A/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsytems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
        4. 8.3.1.4 Processor Subsystem
      2. 8.3.2 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short, Medium, and Long Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.12.4.1 LVDS Interface Configuration

The supported LVDS lane configuration is 1-data lane (LVDS_TXP/M), one Bit Clock lane (LVDS__TXxx_CLKP/M) and one Frame clock lane (LVDS_TXxx_FRCLKP/M). The LVDS interface supports programmable data rates with the maximum being 900Mbps (450MHz DDR Clock).

Note that the bit clock is in DDR format and hence the number of toggles in the clock is equivalent to data.

AWR2944P AWR2E44P LVDS Interface Lane Configuration And Relative Timings Figure 7-20 LVDS Interface Lane Configuration And Relative Timings