JAJSKM7C
November 2020 – July 2022
AWR6843AOP
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
機能ブロック図
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagram
7.2
Signal Descriptions
7.2.1
Pin Functions - Digital and Analog [ALP Package]
7.3
Pin Attributes
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Power-On Hours (POH)
8.4
Recommended Operating Conditions
8.5
Power Supply Specifications
8.6
Power Consumption Summary
8.7
RF Specification
8.8
CPU Specifications
8.9
Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
8.10
Timing and Switching Characteristics
8.10.1
Antenna Radiation Patterns
8.10.1.1
Antenna Radiation Patterns for Receiver
8.10.1.2
Antenna Radiation Patterns for Transmitter
8.10.2
Antenna Positions
8.10.3
Power Supply Sequencing and Reset Timing
8.10.4
Input Clocks and Oscillators
8.10.4.1
Clock Specifications
8.10.5
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.10.5.1
Peripheral Description
8.10.5.2
MibSPI Transmit and Receive RAM Organization
8.10.5.2.1
SPI Timing Conditions
8.10.5.2.2
SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
8.10.5.2.3
SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
8.10.5.3
SPI Peripheral Mode I/O Timings
8.10.5.3.1
SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
8.10.5.4
Typical Interface Protocol Diagram (Peripheral Mode)
8.10.6
LVDS Interface Configuration
8.10.6.1
LVDS Interface Timings
8.10.7
General-Purpose Input/Output
8.10.7.1
Switching Characteristics for Output Timing versus Load Capacitance (CL)
8.10.8
Controller Area Network - Flexible Data-rate (CAN-FD)
8.10.8.1
Dynamic Characteristics for the CANx TX and RX Pins
8.10.9
Serial Communication Interface (SCI)
8.10.9.1
SCI Timing Requirements
8.10.10
Inter-Integrated Circuit Interface (I2C)
8.10.10.1
I2C Timing Requirements
8.10.11
Quad Serial Peripheral Interface (QSPI)
8.10.11.1
QSPI Timing Conditions
8.10.11.2
Timing Requirements for QSPI Input (Read) Timings
8.10.11.3
QSPI Switching Characteristics
8.10.12
ETM Trace Interface
8.10.12.1
ETMTRACE Timing Conditions
8.10.12.2
ETM TRACE Switching Characteristics
8.10.13
Data Modification Module (DMM)
8.10.13.1
DMM Timing Requirements
8.10.14
JTAG Interface
8.10.14.1
JTAG Timing Conditions
8.10.14.2
Timing Requirements for IEEE 1149.1 JTAG
8.10.14.3
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Subsystems
9.3.1
RF and Analog Subsystem
9.3.1.1
Clock Subsystem
9.3.1.2
Transmit Subsystem
9.3.1.3
Receive Subsystem
9.3.2
Processor Subsystem
9.3.3
Automotive Interface
9.3.4
Host Interface
9.3.5
Main Subsystem Cortex-R4F
9.3.6
DSP Subsystem
9.3.7
Hardware Accelerator
9.4
Other Subsystems
9.4.1
ADC Channels (Service) for User Application
9.4.1.1
GP-ADC Parameter
10
Monitoring and Diagnostics
10.1
Monitoring and Diagnostic Mechanisms
10.1.1
Error Signaling Module
11
Applications, Implementation, and Layout
11.1
Application Information
11.2
Reference Schematic
12
Device and Documentation Support
12.1
Device Nomenclature
12.2
Tools and Software
12.3
Documentation Support
12.4
サポート・リソース
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
13.1
Packaging Information
13.2
Tray Information for ALP, 15 × 15 mm
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
ALP|180
サーマルパッド・メカニカル・データ
発注情報
jajskm7c_oa
jajskm7c_pm
12.2
Tools and Software
Models
xWR6843AOP BSDL model
Boundary scan database of testable input and output pins for IEEE 1149.1 of the specific device.
xWR6843AOP IBIS model
IO buffer information model for the IO buffers of the device. For simulation on a circuit board, see IBIS Open Forum.
xWR6843AOP checklist for schematic review, layout review,bringup/wakeup
A set of steps in spreadsheet form to select system functions and pinmux options. Specific EVM schematic and layout notes to apply to customer engineering. A bring up checklist is suggested for customers.