JAJSQU7B
July 2023 – June 2024
AWRL1432
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
機能ブロック図
5
Device Comparison
5.1
Related Products
6
Terminal Configurations and Functions
6.1
Pin Diagrams
6.2
Signal Descriptions
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Power-On Hours (POH)
7.4
Recommended Operating Conditions
7.5
VPP Specifications for One-Time Programmable (OTP) eFuses
7.5.1
Recommended Operating Conditions for OTP eFuse Programming
7.5.2
Hardware Requirements
7.5.3
Impact to Your Hardware Warranty
7.6
Power Supply Specifications
7.6.1
Power Optimized 3.3V I/O Topology
7.6.2
BOM Optimized 3.3V I/O Topology
7.6.3
Power Optimized 1.8V I/O Topology
7.6.4
BOM Optimized 1.8V I/O Topology
7.6.5
System Topologies
7.6.5.1
Power Topologies
7.6.5.1.1
BOM Optimized Mode
7.6.5.1.2
Power Optimized Mode
7.6.6
Internal LDO output decoupling capacitor and layout conditions for BOM optimized topology
7.6.6.1
Single-capacitor rail
7.6.6.1.1
1.2V Digital LDO
7.6.6.2
Two-capacitor rail
7.6.6.2.1
1.2V RF LDO
7.6.6.2.2
1.2V SRAM LDO
7.6.6.2.3
1.0V RF LDO
7.6.7
Noise and Ripple Specifications
7.7
Power Save Modes
7.7.1
Typical Power Consumption Numbers
7.8
Peak Current Requirement per Voltage Rail
7.9
RF Specification
7.10
Supported Front End features
7.11
CPU Specifications
7.12
Thermal Resistance Characteristics
7.13
Timing and Switching Characteristics
7.13.1
Power Supply Sequencing and Reset Timing
7.13.2
Synchronized Frame Triggering
7.13.3
Input Clocks and Oscillators
7.13.3.1
Clock Specifications
7.13.4
MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
7.13.4.1
McSPI Features
7.13.4.2
SPI Timing Conditions
7.13.4.3
SPI—Controller Mode
7.13.4.3.1
Timing and Switching Requirements for SPI - Controller Mode
7.13.4.3.2
Timing and Switching Characteristics for SPI Output Timings—Controller Mode
7.13.4.4
SPI—Peripheral Mode
7.13.4.4.1
Timing and Switching Requirements for SPI - Peripheral Mode
7.13.4.4.2
Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
7.13.5
RDIF Interface Configuration
7.13.5.1
RDIF Interface Timings
7.13.5.2
RDIF Data Format
7.13.6
LIN
7.13.7
General-Purpose Input/Output
7.13.7.1
Switching Characteristics for Output Timing versus Load Capacitance (CL)
7.13.8
Controller Area Network - Flexible Data-rate (CAN-FD)
7.13.8.1
Dynamic Characteristics for the CANx TX and RX Pins
7.13.9
Serial Communication Interface (SCI)
7.13.9.1
SCI Timing Requirements
7.13.10
Inter-Integrated Circuit Interface (I2C)
7.13.10.1
I2C Timing Requirements
7.13.11
Quad Serial Peripheral Interface (QSPI)
7.13.11.1
QSPI Timing Conditions
7.13.11.2
Timing Requirements for QSPI Input (Read) Timings
7.13.11.3
QSPI Switching Characteristics
7.13.12
JTAG Interface
7.13.12.1
JTAG Timing Conditions
7.13.12.2
Timing Requirements for IEEE 1149.1 JTAG
7.13.12.3
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
8
Detailed Description
8.1
Overview
8.2
機能ブロック図
8.3
Subsystems
8.3.1
RF and Analog Subsystem
8.3.2
Clock Subsystem
8.3.3
Transmit Subsystem
8.3.4
Receive Subsystem
8.3.5
Processor Subsystem
8.3.6
Automotive Interface
8.3.7
Host Interface
8.3.8
Application Subsystem
8.3.9
Hardware Accelerator (HWA1.2) Features
8.3.9.1
Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
8.4
Other Subsystems
8.4.1
GPADC Channels (Service) for User Application
8.4.2
GPADC Parameters
8.5
Memory Partitioning Options
8.6
Boot Modes
9
Monitoring and Diagnostics
10
Applications, Implementation, and Layout
10.1
Application Information
10.2
Reference Schematic
11
Device and Documentation Support
11.1
Device Nomenclature
11.2
Tools and Software
11.3
Documentation Support
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
AMF|102
サーマルパッド・メカニカル・データ
発注情報
jajsqu7b_oa
8.3.9
Hardware Accelerator (HWA1.2) Features
Fast FFT computation, with programmable 2
N
sizes, up to 1024-point complex FFT
Internal FFT bit-width of 24 bits for good Signal-to-Quantization-Noise Ratio (SQNR) performance
Fully programmable butterfly scaling at every radix-2 stage for user flexibility
Built-in capabilities for pre-FFT processing – Ex: DC estimation and subtraction
DC estimation & subtraction, Interference estimation & zero-out, Real window, Complex pre-multiplication
Magnitude (absolute value) and Log-magnitude computation
Flexible data flow and data sample arrangement to support efficient multi-dimensional FFT operations and transpose accesses
Chaining and looping mechanism to sequence a set of operations one after another with minimal intervention from the main processor
Peak detection – CFAR (CFAR-CA, CFAR-OS) detector
Basic statistics, including Sum and 1D Max
Compression engine for radar cube memory optimization
Figure 8-6
HWA 1.2 Functional Block Diagram