JAJSPG1A December 2022 – March 2024 AWRL6432
PRODUCTION DATA
STANDARD MODE(1) | FAST MODE | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tc(SCL) | Cycle time, SCL | 10 | 2.5 | μs | ||
tsu(SCLH-SDAL) | Setup time, SCL high before SDA low (for a repeated START condition) | 4.7 | 0.6 | μs | ||
th(SCLL-SDAL) | Hold time, SCL low after SDA low (for a START and a repeated START condition) | 4 | 0.6 | μs | ||
tw(SCLL) | Pulse duration, SCL low | 4.7 | 1.3 | μs | ||
tw(SCLH) | Pulse duration, SCL high | 4 | 0.6 | μs | ||
tsu(SDA-SCLH) | Setup time, SDA valid before SCL high | 250 | 100 | ns | ||
th(SCLL-SDA) | Hold time, SDA valid after SCL low | 0 | 3.45(1) | 0 | 0.9 | μs |
tw(SDAH) | Pulse duration, SDA high between STOP and START conditions | 4.7 | 1.3 | μs | ||
tsu(SCLH-SDAH) | Setup time, SCL high before SDA high (for STOP condition) | 4 | 0.6 | μs | ||
tw(SP) | Pulse duration, spike (must be suppressed) | 0 | 50 | ns | ||
Cb(2)(3) | Capacitive load for each bus line | 400 | 400 | pF |