JAJSPG1A December 2022 – March 2024 AWRL6432
PRODUCTION DATA
Figure 8-5 shows the block diagram for customer programmable processor subsystems in the AWRL6432 device. At a high level there are two customer programmable subsystems, as shown separated by a dotted line in the diagram. The left hand side shows the HWA, a high-bandwidth interconnect for high performance (64-bit, 80MHz), and associated peripherals data transfer. RDIF interface for Measurement data output, L3 Radar data cube memory, the ADC buffers, the CRC engine, and data handshake memory (additional memory provided on interconnect).
The right side of the diagram shows the Main Subsystem. The Main Subsystem is the brain of the device and controls all the device peripherals and house-keeping activities of the device. The Main Subsystem contains Cortex-M4F processor and associated peripherals and house-keeping components such as DMAs, CRC and Peripherals (I2C, UART, SPIs, CAN, PMIC clocking module, PWM, LIN,and others) connected to Main Interconnect through Peripheral Central Resource (PCR interconnect).