JAJSNC1F September   2006  – January 2022

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC
    6. 6.6 Switching Characteristics: AC
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 1024-Bit EPROM
      2. 7.3.2 EPROM Status Memory
      3. 7.3.3 Error Checking
      4. 7.3.4 Customizing the BQ2022A
      5. 7.3.5 Bus Termination
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1  Serial Communication
      2. 7.5.2  Initialization
      3. 7.5.3  ROM Commands
        1. 7.5.3.1 READ ROM Command
        2. 7.5.3.2 SKIP ROM Command
      4. 7.5.4  Memory/Status Function Commands
      5. 7.5.5  READ MEMORY Commands
        1. 7.5.5.1 READ MEMORY/Page CRC
        2. 7.5.5.2 READ MEMORY/Field CRC
      6. 7.5.6  WRITE MEMORY Command
      7. 7.5.7  READ STATUS Command
      8. 7.5.8  WRITE STATUS Command
      9. 7.5.9  PROGRAM PROFILE Byte
      10. 7.5.10 SDQ Signaling
      11. 7.5.11 RESET and PRESENCE PULSE
      12. 7.5.12 WRITE Bit
      13. 7.5.13 READ Bit
      14. 7.5.14 PROGRAM PULSE
      15. 7.5.15 IDLE
      16. 7.5.16 CRC Generation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Circuit Example
        2. 8.2.2.2 SDQ Master Best Practices
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Receiving Notification of Documentation Updates
    3. 11.3 Trademarks
    4. 11.4 サポート・リソース
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.16 CRC Generation

The BQ2022A has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the BQ2022A to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 +1.

Under certain conditions, the BQ2022A also generates an 8-bit CRC value using the same polynomial function just shown and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the BQ2022A. The BQ2022A computes an 8-bit CRC for the command, address, and data bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the bus master to confirm proper transfer. Similarly, the BQ2022A computes an 8-bit CRC for the command and address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/ GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC generator on the BQ2022A is also used to provide verification of error-free data transfer as each page of data from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and for the eight bytes of information in the status memory field.

In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the BQ2022A (for ROM reads) or the 8-bit CRC value computed within the BQ2022A. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. No circuitry on the BQ2022A prevents a command sequence from proceeding if the CRC stored in or calculated by the BQ2022A does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity.

GUID-62E22A1E-DE46-488C-BDA4-FD5D9B086F63-low.gifFigure 7-13 8-Bit CRC Generator Circuit (X8 + X5 + X4 + 1)