7.3.1 EPROM

Table 1 is a memory map of the 1536-bit EPROM section of the bq2026, configured as six pages of 32 bytes each. The 1-byte RAM buffer is an additional register used when programming the memory. Data are first written to the RAM buffer and then verified by reading a 16-bit CRC from the bq2026 that confirms proper receipt of the data. If the buffer contents are correct, a programming pulse is issued and a 1-byte segment of data is written into the selected address in memory. This process ensures data integrity when programming the memory. The details for reading and programming the 1536-bit EPROM portion of the bq2026 are in the Memory and Status Function Commands section of this data sheet.

7.3.2 EPROM Status Memory

In addition to the programmable 1536-bits of memory are eight bytes of status information, the first seven bytes are available to the user, contained in the EPROM status memory. The status memory is accessible with separate commands. The status bytes are EPROM and are read or programmed to indicate various conditions to the software interrogating the bq2026. These general-purpose bytes can be used by the customer to store various information.

7.3.3 Error Checking

Implement error checking by comparing the 16-bit CRC values transmitted by the bq2026. If the two CRC values match, the transmission is error-free. Details are found in the CRC Generation section.

7.4.1 Customizing the bq2026

The 64-bit ID identifies each bq2026 device. The 48-bit serial number is unique and programmed by Texas Instruments. The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis. Contact your Texas Instruments sales representative for more information.

7.4.2 Bus Termination

Because the drive output of the bq2026 is an open-drain, N-channel MOSFET, the host must provide a source current or a 5-kΩ external pullup, as shown in the typical application circuit in Figure 1.

Figure 1. Bus Termination Example for SOT-23 Package

7.4.3 Serial Communication

A host reads, programs, or checks the status of the bq2026 through the hierarchical command structure of the SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or status can be read or modified.

7.4.4 Initialization

Initialization consists of two pulses, the reset and the presence pulses. The host generates the reset pulse, while the bq2026 responds with the presence pulse. The host resets the bq2026 by driving the DATA bus low for at least 480 μs. For more details, see the Reset and Presence Pulse section.

7.4.5 ROM Commands

7.4.5.1 Read ROM

The Read ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code and 48-bit identification number. The Read ROM sequence starts with the host generating the reset pulse of at least 480 μs. The bq2026 responds with a presence pulse. Next, the host continues by issuing the Read ROM command, 33h, and then reads the ROM and CRC byte using the read signaling (see the Write and Read sections) during the data frame.

Figure 3. Read ROM Sequence

7.4.5.2 Match ROM

The Match ROM command, 55h, is used by the host to select a specific SDQ device when the family code and identification number is known. The host issues the Match ROM command followed by the family code, ROM number, and the CRC byte. The device that matches the 64-bit ROM sequence is selected and available to perform subsequent memory and status function commands.

Figure 4. Match ROM Sequence

7.4.5.3 Skip ROM

This Skip ROM command, CCh, allows the host to access the memory and status functions without issuing the 64-bit ROM code sequence. The Skip ROM command is directly followed by a memory or status functions command.

Figure 5. Skip ROM Sequence

7.4.6 Memory and Status Function Commands

Four memory and status function commands allow read and modification of the 1536-bit EPROM data memory or the 7-byte EPROM status memory. There is a Read Memory and Field CRC command, plus the Write Memory, Read Status, and Write Status commands. The bq2026 responds to memory and status function commands only after a device is selected by a ROM command.

7.4.7 Read Memory and Field CRC

To read the memory, the ROM command is followed by the Read Memory command, F0h, followed by the address low byte and then the address high byte.

The host then issues read time slots and receives data from the bq2026, starting at the initial address and continuing until the end of the 1536-bit data field is reached, or until a reset pulse is issued. If reading occurs through the end of memory space, the host may issue sixteen additional read time slots and the bq2026 responds with a 16-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the host, any subsequent read time slots appears as logical 1s until a reset pulse is issued. Any reads ended by a reset pulse prior to reaching the end of memory do not have the 16-bit CRC available.

7.4.8 Read Status

The Read Status command is used to read data from the EPROM status data field. After issuing a ROM command, the host issues the Read Status command, AAh, followed by the address low byte and then the address high byte.

If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the bq2026 starting at the supplied address and continuing until the end of the EPROM Status data field is reached. At that point, the host receives a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte through the final byte.

This feature is provided because the EPROM status information may change over time making it impossible to program the data once and include an accompanying CRC that is always valid. Therefore, the Read Status command supplies a 16-bit CRC that is based on (and always is consistent with) the current data stored in the EPROM status data field.

After the 16-bit CRC is read, the host receives logical 1s from the bq2026 until a reset pulse is issued. The Read Status command sequence can be ended at any point by issuing a reset pulse.

Figure 8. Status Memory Read and Write Flowchart

7.4.9 Write Memory

The Write Memory command is used to program the 1536-bit EPROM memory field. The 1536-bit memory field is programmed in 1-byte segments. Data is first written into an 1-byte RAM buffer. The contents of the RAM buffer is then ANDed with the contents of the EPROM memory field when the programming command is issued.

Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROM command, the host issues the Write Memory command, 0Fh, followed by the low byte and then the high byte of the starting address. The host then transmits 1 byte of data to the bq2026.

a 16-bit CRC is calculated and transmitted based on the command, address and data. If this CRC agrees with the CRC calculated by the host, the host applies the programming voltage for at least 480 μs or t_EPROG.

If at any time during the Write Memory process, the CRC read by the host is incorrect, a reset pulse must be issued, and the entire sequence must be repeated.

The Write Data Memory command sequence can be terminated at any point by issuing a reset pulse except during the program pulse period t_PROG.

For both of these cases, the decision to continue programming is made entirely by the host, because the bq2026 is not able to determine if the 16-bit CRC calculated by the host agrees with the 16-bit CRC calculated by the bq2026.

Prior to programming, bits in the 1536-bit EPROM data field appear as logical 1s.

Figure 9. General Use OTP Memory Read and Write Flowchart

7.4.10 Write Status

The Write Status command is used to program the EPROM Status data field after the bq2026 has been selected by a ROM command

The flow chart in Figure 9 illustrates that the host issues the Write Status command, 55h, followed by the address low byte and then the address high byte followed by the byte of data to be programmed.

If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the programming voltage, V_PP is applied to the SDQ pin for period t_PROG. Prior to programming, the first 7 bytes of the EPROM STATUS data field appear as logical 1s. For each bit in the data byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the EPROM STATUS data field is programmed to a logical 0 after the programming pulse has been applied at the byte location.

After the programming pulse is applied and the data line returns to V_PU, the host issues eight read time slots to verify that the appropriate bits have been programmed. The bq2026 responds with the data from the selected EPROM STATUS address sent least significant bit first. This response should be checked to verify the programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write sequence again. If the bq2026 EPROM data byte programming was successful, the bq2026 automatically increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant byte of the new two-byte address is also loaded into the 16-bit CRC generator as a starting value. The host issues the next byte of data using eight write time slots.

As the bq2026 receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the host reads this 16-bit CRC from the bq2026 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory is programmed.

For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by the host, because the bq2026 is not able to determine if the 16-bit CRC calculated by the host agrees with the 16-bit CRC calculated by the bq2026. If an incorrect CRC is ignored and a program pulse is applied by the host, incorrect programming could occur within the bq2026. Also note that the bq2026 always increments its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Status command, incorrect programming could occur within the bq2026. The Write Status command sequence can be ended at any point by issuing a reset pulse.

7.4.11 SDQ Signaling

All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or to begin the start frame for a bit read. Figure 10 shows the initialization timing, whereas Figure 11 and Figure 12 show that the host initiates each bit by driving the data bus low for the start period, t_WSTRB / t_RSTRB. After the bit is initiated, either the host continues controlling the bus during a write, or the bq2026 responds during a read.

7.4.12 Reset and Presence Pulse

If the data bus is driven low for more than 120 μs, the bq2026 may be reset. Figure 10 shows that if the data bus is driven low for more than 480 μs, the bq2026 resets and indicates that it is ready by responding with a presence pulse.

Figure 10. Reset Timing Diagram

7.4.13 Write

The Write bit timing diagram in Figure 11 shows that the host initiates the transmission by issuing the t_WSTRB portion of the bit and then either driving the data bus low for a write 0, or releasing the data bus for a write 1.

Figure 11. Write Bit Timing Diagram

7.4.14 Read

The Read bit timing diagram in Figure 12 shows that the host initiates the transmission of the bit by issuing the t_RSTRB portion of the bit. The bq2026 then responds by either driving the data bus low to transmit a read 0, or releasing the data bus to transmit a read 1.

Figure 12. Read Bit Timing Diagram

7.4.15 Program Pulse

Figure 13 shows the program pulse timing.

Figure 13. Program Pulse Timing Diagram

7.4.16 Idle

If the bus is high, the bus is in the idle state. Bus transactions can be suspended by leaving the data bus in idle. Bus transactions can resume at any time from the idle state.

7.4.17 CRC Generation

The bq2026 has a 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master computes a CRC value from the first 56 bits of the 64-bit ROM and compares it to the value stored within the bq2026 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is shown in Figure 14.

Under certain conditions, the bq2026 also generates a 16-bit CRC value using the polynomial function is shown in Figure 15 and provides this value to the bus master which validates the transfer of command, address, and data bytes from the bus master to the bq2026. The bq2026 computes a 16-bit CRC for the command, address, and data bytes received for the Write Memory and the Write Status commands, and then outputs this value to the bus master which confirms proper transfer. Similarly, the bq2026 computes a 16-bit CRC for the command and address bytes received from the bus master for the Read Memory, and Read Status commands to confirm that these bytes have been received correctly.

In each case, where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function in Figure 14 or Figure 15 and compares the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the bq2026 (for ROM reads) or the 16-bit CRC value computed within the bq2026. The comparison of CRC values and the decision to continue with an operation are determined entirely by the bus master. No circuitry on the bq2026 prevents a command sequence from proceeding if the CRC stored in or calculated by the bq2026 does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity.

Figure 14. 8-bit CRC Generator Circuit (X⁸ + X⁵ + X⁴ + 1) for Serial Number Read

SPACER

Figure 15. 16-bit CRC Generator Circuit (X¹⁶ + X¹⁵ + X² + 1) for Memory Interface