JAJSDJ9D April   2016  – January 2019

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Operational Characteristics (Protection Circuits Waveforms)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Down or Undervoltage Lockout (UVLO)
      2. 8.3.2 Power-up
      3. 8.3.3 Sleep Mode
      4. 8.3.4 New Charge Cycle
      5. 8.3.5 Overvoltage-Protection (OVP) – Continuously Monitored
      6. 8.3.6 CHG Terminal Indication
    4. 8.4 Device Functional Modes
      1. 8.4.1  CHG LED Pull-up Source
      2. 8.4.2  IN-DPM (VIN-DPM or IN-DPM)
      3. 8.4.3  OUT
      4. 8.4.4  ISET
      5. 8.4.5  TS
      6. 8.4.6  Termination and Timer Disable Mode (TTDM) - TS Terminal High
      7. 8.4.7  Timers
      8. 8.4.8  Termination
      9. 8.4.9  Battery Detect Routine
      10. 8.4.10 Refresh Threshold
      11. 8.4.11 Starting a Charge on a Full Battery
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculations
          1. 9.2.2.1.1 Program the Fast Charge Current, ISET:
          2. 9.2.2.1.2 Pre-Charge and Termination Current Thresholds, ITERM, and PRE-CHG
          3. 9.2.2.1.3 TS Function
          4. 9.2.2.1.4 CHG
        2. 9.2.2.2 Selecting In and Out Terminal Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Leakage Current Effects on Battery Capacity
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
UVLO Undervoltage lockout exit VIN: 0 V to 4 V 3.15 3.3 3.45 V
VHYS-UVLO Hysteresis on VUVLO_RISE falling VIN: 0 V to 4 V, VUVLO_FALL = VUVLO_RISE – VHYS-UVLO 175 227 280 mV
VIN-DT Input power good detection threshold is VOUT+VIN-DT (Input power good if VIN > VOUT + VIN-DT); VOUT = 3.6 V, VIN: 3.5 V to 4 V 30 80 145 mV
VHYS-INDT Hysteresis on VIN-DT falling VOUT = 3.6 V, VIN: 4 V to 3.5 V 31 mV
VOVP Input overvoltage protection threshold VIN: 5 V to 12 V 6.5 6.65 6.8 V
VHYS-OVP Hysteresis on OVP VIN: 11 V to 5 V 95 mV
VIN-DPM Adaptor low input voltage protection. Restricts lout at VIN-DPM Feature active in adaptor mode; Limit Input Current to 50 mA; VOUT = 3.5 V; RISET = 825 4.24 4.3 4.46 V
ISET SHORT CIRCUIT TEST
RISET_SHORT Highest resistance considered a fault (short). Monitored for IOUT>90mA RISET: 250 Ω to 540 Ω, Iout latches off. Cycle power to reset 500 Ω
IOUT_CL Maximum OUT current limit regulation (clamp) VIN = 5 V, VOUT = 3.6 V, RISET: 250 Ω to 540 Ω, Iout latches off after tDGL-SHORT 1.05 1.4 A
BATTERY SHORT PROTECTION
VOUT(SC) OUT terminal short-circuit detection threshold/precharge threshold Vout:3V to 0.5V, no deglitch 0.75 0.8 0.85 V
VOUT(SC-HYS) OUT terminal short hysteresis Recovery ≥ VOUT(SC) + VOUT(SC-HYS); Rising, no deglitch 77 mV
IOUT(SC) Source current to OUT terminal during short-circuit detection 10 15 20 mA
QUIESCENT CURRENT
IOUT(PDWN) Battery current into OUT terminal VIN = 0V 1 µA
IOUT(DONE) OUT pin current, charging terminated VIN = 6 V, VBAT > VBAT(REG), net current is into OUT pin 6 µA
IIN(STDBY) Standby current into IN pin TS = Low, VIN ≤ 6 V 125 µA
ICC Active supply current, IN pin TS = Low, VIN = 6 V, no load on OUT pin, VBAT > VBAT(REG) 1000 µA
BATTERY CHARGER FAST-CHARGE
VOUT(REG) Battery regulation voltage VREG = 4.2 V, IL = 25 mA, VIN = 5.5 V 4.16 4.2 4.23 V
IOUT(RANGE) Programmed output fast charge current range VOUT(REG) > VOUT > VLOWV; VIN = 5 V,  RISET = 0.675 to 52 kΩ 10 800 mA
VDO(IN-OUT) Drop-Out, VIN – VOUT Adjust VIN down until IOUT = 0.5 A, VOUT = 4.15 V, RISET = 1.08kΩ 325 550 mV
IOUT Output fast charge formula VOUT(REG) > VOUT > VLOWV; VIN = 5 V KISET/
RISET		 KISET/
RISET		 KISET/
RISET		 A
KISET Fast charge current factor KISET (60mA < I <1000mA) 490 540 590 AΩ
KISET (25mA < I < 60mA) 470 527 605
KISET (10mA < I < 25mA) 340 520 685
PRECHARGE
VLOWV Pre-charge to fast-charge transition threshold 2.4 2.5 2.6 V
Pre-charge Default pre-charge current VBAT < VLOWV, ICHG = 50 mA 18 20 22 %ISET
TERMINATION
%TERM Termination Threshold Current, default setting VOUT > VRCH; RISET = 1 kΩ 9 10 11 %IOUT-CC
RECHARGE OR REFRESH
VRCH Recharge detection threshold VIN = 5 V, VTS = 0.5 V, VOUT = 4.25 V to VRCH VO(REG) - 120 mV VO(REG) - 95 mV VO(REG) - 70 mV mV
BATT DETECT
VREG-BD VOUT Reduced regulation during battery detect VIN = 5 V, VTS = 0.5 V, battery absent VO(REG) - 450 mV VO(REG) - 400 mV VO(REG) - 350 mV mV
IBD-SINK Sink current during VREG-BD 7 10 mA
VBD-HI High battery detection threshold VIN = 5 V, VTS = 0.5 V, battery absent VO(REG) - 150 mV VO(REG) - 100 mV VO(REG) - 50 mV V
VBD-LO Low battery detection threshold VREG-BD+0.50 VREG-BD+0.1 VREG-BD+0.15 V
BATTERY-PACK NTC MONITOR
INTC 50µA NTC bias current 48 50 53 µA
INTC-DIS-10K 10K NTC bias current when charging is disabled VTS = 0 V 27 30 34 µA
INTC-FLDBK -10K INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM VTS = 1.525 V 4 5 6.5 µA
VTTDM(TS) Termination and timer disable mode-Threshold-Enter VTS: 0.5 V to 1.7 V; timer held in reset 1550 1600 1650 mV
IHYS-TTDM(TS) Hysteresis exiting TTDM VTS: 1.7 V to 0.5 V; timer enabled 100 mV
VCLAMP(TS) TS maximum voltage clamp VTS = Open (float) 1800 1950 2000 mV
VTS_I-FLDBK TS voltage where INTC is reduce to keep thermistor from entering TTDM INTC adjustment (90 to 10%; 45 to 6.6 µs) takes place near this spec threshold. VTS: 1.425 V to 1.525 V 1475 mV
CTS Optional capacitance – ESD 0.22 µF
VTS-0C Low temperature CHG pending Normal temperature charging to pending; VTS: 1 V to 1.5 V 1220 1250 1280 mV
VHYS-0C Hysteresis at 0°C Charge pending to normal temperature charging; VTS: 1.5 V to 1 V 100 mV
VTS-45C High temperature CHG disable Normal temperature charging to pending; VTS: 0.5 V to 0.2 V 260 275 290 mV
VHYS-45C Hysteresis at 45°C Charge pending to normal temperature charging; VTS: 0.2 V to 0.5 V 20 mV
VTS-EN-10K Charge enable threshold (10k NTC) VTS: 0 V to 0.175 V 80 88 96 mV
VTS-DIS_HYS-10K HYS below VTS-EN-10k to disable (10k NTC) VTS: 0.125 V to 0 V 12 mV
THERMAL REGULATION
TJ(REG) Temperature regulation limit 125 °C
TJ(OFF) Thermal shutdown temperature 155
TJ(OFF-HYS) Thermal shutdown hysteresis 20
CHG INDICATION
VOL Output Low Voltage-CHG FET on - first charge after power-up ISINK = 5 mA 0.4 V
ILEAK Leakage current into IC VCHG = 5 V 1 µA