JAJSE21B October   2017  – November 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Power On
      3. 9.3.3 Overvoltage Protection (OVP)
      4. 9.3.4 Dynamic Power-path Management
        1. 9.3.4.1 Input Source Connected (Adapter or USB)
          1. 9.3.4.1.1 Input DPM Mode (VIN-DPM)
          2. 9.3.4.1.2 DPPM Mode
          3. 9.3.4.1.3 Battery Supplement Mode
        2. 9.3.4.2 Input Source Not Connected
      5. 9.3.5 Battery Charging
        1. 9.3.5.1 Charge Current Translator
        2. 9.3.5.2 Battery Detection And Recharge
        3. 9.3.5.3 Battery Disconnect (SYSOFF Input)
        4. 9.3.5.4 Dynamic Charge Timers (TMR Input)
        5. 9.3.5.5 Status Indicators (PGOOD, CHG)
        6. 9.3.5.6 Thermal Regulation And Thermal Shutdown
      6. 9.3.6 Battery Pack Temperature Monitoring
      7. 9.3.7 Half-Wave Adaptors
    4. 9.4 Device Functional Modes
      1. 9.4.1 Sleep Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application – bq24079QW-Q1 Charger Design Example
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Calculations
          1. 10.2.2.1.1 Program the Fast Charge Current (ISET):
          2. 10.2.2.1.2 Program the Input Current Limit (ILIM)
          3. 10.2.2.1.3 Program 6.25-hour Fast-Charge Safety Timer (TMR)
        2. 10.2.2.2 TS Function
        3. 10.2.2.3 CHG and PGOOD
        4. 10.2.2.4 System ON/OFF (SYSOFF)
        5. 10.2.2.5 Selecting In, Out And Bat Pin Capacitors
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Package
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGT|16
サーマルパッド・メカニカル・データ
発注情報

9.3.1 Undervoltage Lockout (UVLO)

The bq24079QW-Q1 remains in power down mode when the input voltage at the IN pin is below the undervoltage threshold (UVLO).

During the power down mode, the host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and OUT pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT to OUT is ON. (If SYSOFF is high, Q2 is off). During power down mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.