11.1 Layout Guidelines

It is important to pay special attention to the PCB layout. The following provides some guidelines:

• To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2408x, with short trace runs to both IN, OUT and GND (thermal pad).
• All low-current GND connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small signal ground path and the power ground path.
• The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces.
• The bq2408x family are packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. Full PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application Note, SLUA271.

11.2 Layout Example

Figure 23. bq2408x PCB Layout

11.3 Thermal Considerations

The bq2408x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application Note, SLUA271.

The most common measure of package thermal performance is thermal impedance (θ_JA ) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). Use Equation 13 as the mathematical expression for θ_JA:

Equation 13.

where

• T_J = chip junction temperature
• T_A = ambient temperature
• P = device power dissipation

Factors that can greatly influence the measurement and calculation of θ_JA include:

• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET. Use Equation 14 to calculate the device power dissipation when a battery pack is being charged:

Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See the charging profile, Figure 8.

If the board thermal design is not adequate the programmed fast charge rate current may not be achieved under maximum input voltage and minimum battery voltage, as the thermal loop can be active effectively reducing the charge current to avoid excessive IC junction temperature.