SLUS606P June   2004  – November 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PWM Controller
      2. 8.3.2  Temperature Qualification
      3. 8.3.3  Battery Preconditioning (Precharge)
      4. 8.3.4  Battery Charge Current
      5. 8.3.5  Battery Voltage Regulation
      6. 8.3.6  Charge Termination and Recharge
      7. 8.3.7  Sleep Mode
      8. 8.3.8  Charge Status Outputs
      9. 8.3.9  PG Output
      10. 8.3.10 CE Input (Charge Enable)
      11. 8.3.11 Timer Fault Recovery
      12. 8.3.12 Output Overvoltage Protection (Applies to All Versions)
      13. 8.3.13 Functional Description For System-Controlled Version (bq2411x)
      14. 8.3.14 Precharge and Fast-Charge Control
      15. 8.3.15 Charge Termination and Safety Timers
      16. 8.3.16 Battery Detection
        1. 8.3.16.1 Battery Detection Example
      17. 8.3.17 Current Sense Amplifier
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor, Capacitor, and Sense Resistor Selection Guidelines
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6 Pin Configuration and Functions

RHL Package
20-Pin VQFN
Top View
bq24100 bq24103 bq24103A bq24104 bq24105 bq24108 bq24109 bq24113 bq24113A bq24115 pinout_lus606.gif
bq24100, 03, 03A, 04, 05, 08, 09, 13, 13A, 15

Pin Functions

PIN I/O DESCRIPTION
NAME bq24100,
bq24108,
bq24109		 bq24103,
bq24103A
bq24104		 bq24105 bq24113, bq24113A bq24115
BAT 14 14 14 14 14 I Battery voltage sense input. Bypass it with a 0.1 μF capacitor to PGND if there are long inductive leads to battery.
CE 16 16 16 16 16 I Charger enable input. This active low input, if set high, suspends charge and places the device in the low-power sleep mode. Do not pull up this input to VTSB.
CELLS 13 13 I Available on parts with fixed output voltage. Ground or float for single-cell operation (4.2 V). For two-cell operation (8.4 V) pull up this pin with a resistor to VCC.
CMODE 7 7 I Charge mode selection: low for precharge as set by ISET2 pin and high (pull up to VTSB or <7 V) for fast charge as set by ISET1.
FB 13 13 I Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider powered from the battery terminals to this node to adjust the output battery voltage regulation.
IN 3, 4 3, 4 3, 4 3, 4 3, 4 I Charger input voltage.
ISET1 8 8 8 8 8 I/O Charger current set point 1 (fast charge). Use a resistor to ground to set this value.
ISET2 9 9 9 9 9 I/O Charge current set point 2 (precharge and termination), set by a resistor connected to ground. A low-level CMODE signal selects the ISET2 charge rate, but if the battery voltage reaches the regulation set point, bqSWITCHER™ changes to voltage regulation regardless of CMODE input.
N/C 13 19 19 - No connection. This pin must be left floating in the application.
OUT 1 1 1 1 1 O Charge current output inductor connection. Connect a zener TVS diode between OUT pin and PGND pin to clamp the voltage spike to protect the power MOSFETs during abnormal conditions.
20 20 20 20 20 O
PG 5 5 5 5 5 O Power-good status output (open drain). The transistor turns on when a valid VCC is detected. It is turned off in the sleep mode. PG can be used to drive a LED or communicate with a host processor.
PGND 17,18 17,18 17,18 17,18 17, 18 Power ground input
SNS 15 15 15 15 15 I Charge current-sense input. Battery current is sensed via the voltage drop developed on this pin by an external sense resistor in series with the battery pack. A 0.1-μF capacitor to PGND is required.
STAT1 2 2 2 2 2 O Charge status 1 (open-drain output). When the transistor turns on indicates charge in process. When it is off and with the condition of STAT2 indicates various charger conditions (See Table 1)
STAT2 19 19 19 O Charge status 2 (open-drain output). When the transistor turns on indicates charge is done. When it is off and with the condition of STAT1 indicates various charger conditions (See Table 1)
TS 12 12 12 12 12 I Temperature sense input. This input monitors its voltage against an internal threshold to determine if charging is allowed. Use an NTC thermistor and a voltage divider powered from VTSB to develop this voltage. (See Figure 4)
TTC 7 7 7 I Timer and termination control. Connect a capacitor from this node to GND to set the bqSWITCHER™ timer. When this input is low, the timer and termination detection are disabled.
VCC 6 6 6 6 6 I Analog device input. A 0.1 μF capacitor to VSS is required.
VSS 10 10 10 10 10 Analog ground input
VTSB 11 11 11 11 11 O TS internal bias regulator voltage. Connect capacitor (with a value between a 0.1-μF and 1-μF) between this output and VSS.
Exposed Thermal
Pad		 Pad Pad Pad Pad Pad There is an internal electrical connection between the exposed thermal pad and VSS. The exposed thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. The power pad can be used as a star ground connection between VSS and PGND. A common ground plane may be used. VSS pin must be connected to ground at all times.