11.1 Layout Guidelines

It is important to pay special attention to the PCB layout. The following provides some guidelines:

• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed as close as possible to the bqSWITCHER. The output inductor should be placed directly above the IC and the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area from the OUT pin through the LC filter and back to the PGND pin. The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the R_SNS back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers. BAT and SNS traces should be away from high di/dt traces such as the OUT pin. Use an optional capacitor downstream from the sense resistor if long (inductive) battery leads are used.
• Place all small-signal components (C_TTC, RSET1/2 and TS) close to their respective IC pin (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias (3 vias per capacitor for power-stage capacitors, 3 vias for the IC PGND, 1 via per capacitor for small-signal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is not a ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. The thermal vias in the IC PowerPAD™ provide the return-path connection.
• The bqSWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the PCB. Full PCB design guidelines for this package are provided in the application report entitled: QFN/SON PCB Attachment, SLUA271. Six 10-13 mil vias are a minimum number of recommended vias, placed in the IC's power pad, connecting it to a ground thermal plane on the opposite side of the PWB. This plane must be at the same potential as V_SS and PGND of this IC.
• See user's guide, Using the bq241xx (bqSWITCHER™), SLUU200 for an example of good layout.

11.2 Layout Example

Figure 25. bq2412x PCB Layout

11.3 Thermal Considerations

The SWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled: QFN/SON PCB Attachment , SLUA271.

The most common measure of package thermal performance is thermal impedance (θ_JA) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θ_JA is:

Equation 23.

where

• T_J = chip junction temperature
• T_A = ambient temperature
• P = device power dissipation

Factors that can greatly influence the measurement and calculation of θ_JA include:

• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether or not other surfaces are in close proximity to the device being tested

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power FET. It can be calculated from the following equation:

P = [Vin × lin - Vbat × Ibat]

Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. (See Figure 8).