SLUSAB0D October   2010  – April 2016

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparisons
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Protection
        1. 9.3.1.1 Input Overvoltage Protection
        2. 9.3.1.2 Bad Adaptor Detection/Rejection
        3. 9.3.1.3 Sleep Mode
        4. 9.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)
      2. 9.3.2 Battery Protection
        1. 9.3.2.1 Output Overvoltage Protection
        2. 9.3.2.2 Battery Short Protection
        3. 9.3.2.3 Battery Detection at Power Up in 15-minute Mode (bq24153A/6A only)
        4. 9.3.2.4 Battery Detection in Host Mode
      3. 9.3.3 15-Minute Safety Timer and 32-second Watchdog Timer in Charge Mode
      4. 9.3.4 USB Friendly Power Up
      5. 9.3.5 Input Current Limiting at Power Up
    4. 9.4 Device Functional Modes
      1. 9.4.1 Charge Mode Operation
        1. 9.4.1.1 Charge Profile
      2. 9.4.2 PWM Controller in Charge Mode
      3. 9.4.3 Battery Charging Process
      4. 9.4.4 Thermal Regulation and Protection
      5. 9.4.5 Charge Status Output, STAT Pin
      6. 9.4.6 Control Bits in Charge Mode
        1. 9.4.6.1 CE Bit (Charge Mode)
        2. 9.4.6.2 RESET Bit
        3. 9.4.6.3 OPA_Mode Bit
      7. 9.4.7 Control Pins in Charge Mode
        1. 9.4.7.1 CD Pin (Charge Disable)
        2. 9.4.7.2 SLRST Pin (Safety Limit Register 06H Reset, bq24156A/9 only)
      8. 9.4.8 BOOST Mode Operation (bq24153A/8 only)
        1. 9.4.8.1 PWM Controller in Boost Mode
        2. 9.4.8.2 Boost Start Up
        3. 9.4.8.3 PFM Mode at Light Load
        4. 9.4.8.4 Safety Timer in Boost Mode
        5. 9.4.8.5 Protection in Boost Mode
          1. 9.4.8.5.1 Output Overvoltage Protection
          2. 9.4.8.5.2 Output Overload Protection
          3. 9.4.8.5.3 Battery Overvoltage Protection
        6. 9.4.8.6 STAT Pin in Boost Mode
      9. 9.4.9 High Impedance (HI-Z) Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
        1. 9.5.1.1 F/S Mode Protocol
        2. 9.5.1.2 H/S Mode Protocol
        3. 9.5.1.3 I2C Update Sequence
        4. 9.5.1.4 Slave Address Byte
        5. 9.5.1.5 Register Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 Status/Control Register [Memory Location: 00, Reset State: x1xx 0xxx]
      2. 9.6.2 Control Register [Memory Location: 01, Reset State: 0011 0000]
      3. 9.6.3 Control/Battery Voltage Register [Memory Location: 02, Reset State: 0000 1010]
      4. 9.6.4 Vender/Part/Revision Register [Memory Location: 03, Reset State: 0101 000x]
      5. 9.6.5 Battery Termination/Fast Charge Current Register [Memory Location: 04, Reset State: 0000 000]
      6. 9.6.6 Special Charger Voltage/Enable Pin Status Register [Memory location: 05, Reset state: 001X X100]
      7. 9.6.7 Safety Limit Register [Memory location: 06, Reset state: 01000000]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Systems Design Specifications
        2. 10.2.2.2 Charge Current Sensing Resistor Selection Guidelines
        3. 10.2.2.3 Output Inductor and Capacitance Selection Guidelines
      3. 10.2.3 Application Curves
    3. 10.3 System Example
  11. 11Power Supply Recommendations
    1. 11.1 System Load After Sensing Resistor
    2. 11.2 System Load Before Sensing Resistor
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Current Path
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Summary
      1. 14.1.1 Chip Scale Packaging Dimensions

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

It is important to pay special attention to the PCB layout. The following provides some guidelines:

  • To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper layout to minimize high frequency current path loop is critical. (See Figure 39.) The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers (do not route the sense leads through a high-current path). (See Figure 40.)
  • Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths.
  • The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for small-signal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue, and having the components segregated minimizes coupling between signals.
  • The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET.
  • Place 4.7μF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. Place 1μF input capacitor as close to VBUS pin and PGND pin as possible to make high frequency current loop area as small as possible (see Figure 41).

12.1.1 Current Path

bq24153A bq24156A bq24158 bq24159 cur_pth_lus931.gif Figure 39. High Frequency Current Path

12.2 Layout Example

bq24153A bq24156A bq24158 bq24159 pcb_layout_lus824.gif Figure 40. Sensing Resistor PCB Layout
bq24153A bq24156A bq24158 bq24159 icp_lusa27.gif Figure 41. Input Capacitor Position and PCB Layout Example