SLUSAW5B January   2012  – December 2014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Power Up
        1. 9.3.1.1 Power-On-Reset (POR)
        2. 9.3.1.2 Power Up from Battery without DC Source
          1. 9.3.1.2.1 BATFET Turn Off
          2. 9.3.1.2.2 Shipping Mode
        3. 9.3.1.3 Power Up from DC Source
          1. 9.3.1.3.1 REGN LDO
          2. 9.3.1.3.2 Input Source Qualification
          3. 9.3.1.3.3 Input Current Limit Detection
          4. 9.3.1.3.4 D+/D- Detection Sets Input Current Limit in bq24190
          5. 9.3.1.3.5 PSEL/OTG Pins Set Input Current Limit in bq24192, bq24192I
          6. 9.3.1.3.6 HIZ State wth 100mA USB Host
          7. 9.3.1.3.7 Force Input Current Limit Detection
        4. 9.3.1.4 Converter Power-Up
        5. 9.3.1.5 Boost Mode Operation from Battery
      2. 9.3.2 Power Path Management
        1. 9.3.2.1 Narrow VDC Architecture
        2. 9.3.2.2 Dynamic Power Management
        3. 9.3.2.3 Supplement Mode
      3. 9.3.3 Battery Charging Management
        1. 9.3.3.1 Autonomous Charging Cycle
        2. 9.3.3.2 Battery Charging Profile
        3. 9.3.3.3 Battery Path Impedance IR Compensation
        4. 9.3.3.4 Thermistor Qualification
          1. 9.3.3.4.1 Cold/Hot Temperature Window
        5. 9.3.3.5 Charging Termination
          1. 9.3.3.5.1 Termination when REG02[0] = 1
          2. 9.3.3.5.2 Termination when REG05[6] = 1
        6. 9.3.3.6 Charging Safety Timer
        7. 9.3.3.7 USB Timer when Charging from USB100mA Source
      4. 9.3.4 Status Outputs (PG, STAT, and INT)
        1. 9.3.4.1 Power Good Indicator (PG)
        2. 9.3.4.2 Charging Status Indicator (STAT)
        3. 9.3.4.3 Interrupt to Host (INT)
      5. 9.3.5 Protections
        1. 9.3.5.1 Input Current Limit on ILIM
        2. 9.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 9.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 9.3.5.3.1 Input Over-Voltage (ACOV)
          2. 9.3.5.3.2 System Over-Voltage Protection (SYSOVP)
        4. 9.3.5.4 Voltage and Current Monitoring in Boost Mode
          1. 9.3.5.4.1 VBUS Over-Voltage Protection
        5. 9.3.5.5 Battery Protection
          1. 9.3.5.5.1 Battery Over-Current Protection (BATOVP)
          2. 9.3.5.5.2 Charging During Battery Short Protection
          3. 9.3.5.5.3 System Over-Current Protection
      6. 9.3.6 Serial Interface
        1. 9.3.6.1 Data Validity
        2. 9.3.6.2 START and STOP Conditions
        3. 9.3.6.3 Byte Format
        4. 9.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.6.5 Slave Address and Data Direction Bit
          1. 9.3.6.5.1 Single Read and Write
          2. 9.3.6.5.2 Multi-Read and Multi-Write
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
        1. 9.4.1.1 Plug in USB100mA Source with Good Battery
        2. 9.4.1.2 USB Timer when Charging from USB 100-mA Source
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
        1. 9.5.1.1  Input Source Control Register REG00 (bq24190, bq24192 reset = 00110000, or 30; bq24192I reset = 00111000, or 38)
        2. 9.5.1.2  Power-On Configuration Register REG01 (reset = 00011011, or 1B)
        3. 9.5.1.3  Charge Current Control Register REG02 (bq24190, bq24192 reset = 01100000, or 60; bq24192I reset = 00100000, or 20)
        4. 9.5.1.4  Pre-Charge/Termination Current Control Register REG03 (reset = 00010001, or 11)
        5. 9.5.1.5  Charge Voltage Control Register REG04 (bq24190, bq241192 reset = 10110010, or B2; bq24192I reset = 10011010, or 9A)
        6. 9.5.1.6  Charge Termination/Timer Control Register REG05 (reset = 10011010, or 9A)
        7. 9.5.1.7  IR Compensation / Thermal Regulation Control Register REG06 (reset = 00000011, or 03)
        8. 9.5.1.8  Misc Operation Control Register REG07 (reset = 01001011, or 4B)
        9. 9.5.1.9  System Status Register REG08
        10. 9.5.1.10 Fault Register REG09
        11. 9.5.1.11 Vender / Part / Revision Status Register REG0A (bq24190 reset = 00100011, or 23; bq24192 reset = 00101011, or 2B; bq24192I reset = 00001011, or 0B)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
      3. 10.2.3 Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 51) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

  1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
  2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
  4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
  5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
  6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
  7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  8. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the VQFN information, refer to SCBA017 and SLUA271.

High_Frequency_Current_Path_SLUSAW5.gifFigure 51. High Frequency Current Path

12.2 Layout Example

layout_ex_slusbp6.gifFigure 52. Layout Example Diagram