SLUSA76B December   2010  – January 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage-Based Dynamic Power Management (VBUS-DPM)
      2. 8.3.2 CHG Pin Indication
      3. 8.3.3 CHG and PG LED Pull-Up Source
      4. 8.3.4 Power Good Indication (PG)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down or Undervoltage Lockout (UVLO)
      2. 8.4.2 Operation Mode Detection and Transition
      3. 8.4.3 Sleep Mode
      4. 8.4.4 Load Mode
      5. 8.4.5 Charge Mode
        1. 8.4.5.1  Overvoltage Protection (OVP) - Continuously Monitored
        2. 8.4.5.2  Power Up
        3. 8.4.5.3  Battery Detect Routine
        4. 8.4.5.4  New Charge Cycle
        5. 8.4.5.5  BAT Output
        6. 8.4.5.6  Fast Charge Current (IOUT)
        7. 8.4.5.7  Termination
        8. 8.4.5.8  Timers
        9. 8.4.5.9  Battery Temperature Monitoring
        10. 8.4.5.10 Limited Power Charge Mode - TS Pin High
      6. 8.4.6 Suspend Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Input Voltage VBUS (with respect to VSS) –0.3 20 V
BAT (with respect to VSS) –0.3 7
VDPM, VTSB, ISET, TS, EN, CHG, PG (with respect to VSS) –0.3 7
Input Current VBUS 1.25 A
Output Current (Continuous) BAT 1.25 A
Output Sink Current CHG, PG 15 mA
Junction temperature, TJ –40 150 °C
Storage Temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VBUS Voltage range 3.5 18 V
Operating voltage range, Restricted by UVLO and OVP 3.5 7.0
IBUS Input current, VBUS pin 0.8 A
IBAT Current, BAT pin 0.8 A
TJ Junction Temperature 0 125 °C
RVDPM Programs input voltage regulation Thresholds 1k 10k Ω
RISET Fast-charge current programming resistor 675 10.8K Ω
VTS Voltage across NTC Thermistor for charging 12 57 %VTSB
CBAT By-pass capacitor on BAT pin 1 10 µF
CVBUS By-pass capacitor on VBUS pin 1 10 µF
CVTSB By-pass capacitor on VTSB pin 0.1 µF

7.4 Thermal Information

THERMAL METRIC(1) bq24210 UNIT
DQC
10 PINS
RθJA Junction-to-ambient thermal resistance 60.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.1
RθJB Junction-to-board thermal resistance 22.2
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 22.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS=5 V, charge mode (EN = Low) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VUVLO Undervoltage lock-out Exit VBUS: 0 V → 4 V 3.15 3.3 3.45 V
VHYS_UVLO Hysteresis on VUVLO Falling VBUS: 4 V→0 V,VUVLO_FALL = VUVLO–VHYS-UVLO 175 227 280 mV
VBUS-DT Input Power Good detection threshold VBUS above BAT (Input power good if VBUS > BAT + VBUS-DT);
BAT = 3.6 V, VBUS: 3.5 V → 4 V		 150 200 250 mV
VHYS-VBUSDT Hysteresis on VBUS-DT Falling BAT = 3.6 V, VBUS: 4 V → 3.5 V 250 mV
tDGL(PG_PWR) Deglitch time on exiting sleep Time measured from VBUS: 0 V → 5 V 1-μs rise-time
to PG = Low, BAT=3.6 V		 90 µs
tDGL(PG_NO-PWR) Deglitch time on VHYS-VBUSDT power down. Same as entering sleep. Time measured from VBUS: 5 V → 3.2 V 1-μs fall-time
to PG = Open Circuit		 29 ms
VOVP Input overvoltage protection threshold VBUS: 5 V → 8 V 7.3 7.5 7.7 V
VHYS-OVP Hysteresis on OVP VBUS: 11 V → 5 V 200 mV
tBLK(OVP) Input overvoltage blanking time VBUS: 5 V → 12 V 113 μs
tDGL(PG_OVP) Deglitch time exiting OVP Time measured from VBUS: 12 V → 5 V 1-μs fall-time
to PG = Low		 5 ms
VBUS-DPM Input voltage regulation threshold. Restricts lout at VBUS-DPM Programmable, the programming resistor at VDPM pin RVDPM = 1kΩ 3.55 3.65 3.75 V
Programmable, the programming resistor at VDPM pin RVDPM = 10kΩ 4.8 5 5.1
KVBUS_DPM Term Factor BAT > VLOWV, VBUS = 5 V, RVDPM = 1 kΩ to 10 kΩ;
RVDPM = KVBUS_DPM × (VBUS_DPM–VBUS_DPM_1)		 0.135 0.15 0.165 V/KΩ
VBUS_DPM_1 Initial voltage for VBUS_DPM threshold setting BAT > VLOWV, VBUS = 5 V, RVDPM = 1 kΩ to 10 kΩ 3.41 3.5 3.59 V
VBUS_DPM_0 VBUS_DPM threshold when VDPM is shorted to VSS BAT > VLOWV, VBUS = 5 V, RVDPM < 500 Ω 3.65 V
IVBUS_DPM Current for programming VBUS_DPM 75 μA
VTRK Battery voltage tracking threshold for VBUS DPM loop VDPM pin Float (open circuit,
RTS > 500 kΩ), BAT rising		 BAT ≤ 3.6 V 3.65 3.7 3.75 V
BAT > 3.6 V BAT
+0.07		 BAT
+0.10		 BAT
+0.145
VTRK_HYS Hysteresis for VTRK BAT falling 60 mV
VBUS_CHG Input voltage to enable CHG pin, VBUS-VBUS_DPM or VBUS-VTRK EN=LOW, VBUS rising above VIN DPM threshold 80 mV
VBUS_CHG_HYS Hysteresis for VBUS_CHG EN=LOW, VBUS falling 160 mV
tDGL_CHG Deglitch time for CHG pin status change 5 mS
ISET SHORT CIRCUIT TEST
RISET_MAX Highest Resistor value considered a fault (short). Monitored for Iout>90mA Riset: 600 Ω → 250 Ω, Iout latches off. Cycle power to Reset. Fault range >1.10 A 200 250 300 Ω
tDGL-SHORT Deglitch time transition from ISET Short to Iout Disable Clear fault by cycling IN or CHGEN 1 ms
IOUT_CL Maximum OUT current limit regulation (Clamp) 0.95 1.4 A
BATTERY SHORT PROTECTION
IBAT(SC) Source current out BAT pin during short-circuit detection 13 17 21 mA
BAT(SC) BAT pin short-circuit detection threshold/ Pre-Charge Threshold BAT:3 V → 0.5 V, no deglitch 0.75 0.8 0.85 V
BAT(SC-HYS) BAT pin Short Hysteresis Recovery → BAT(SC) + BAT(SC-HYS); Rising, no Deglitch 77 mV
QUIESCENT CURRENT
IOUT(DONE) BAT pin current, charging terminated EN=Low, VBUS = 6 V, Terminated 9 μA
IOUT(STDBY) Suspend current into BAT pin EN=High, VBUS =0 V, BAT = 4.2 V 5 μA
IBUS(STDBY) Suspend current into VBUS pin EN=High, VBUS ≤ 6 V 100 175 μA
ICC Active supply current, VBUS pin No load on VTSB pin, EN=Low, VBUS = 6 V, no load on BAT pin,
BAT > VO(REG), IC enabled		 0.8 1.2 mA
ICC_REV Active supply current, BAT pin in load mode EN = Low, BAT = 4 V, no load on VBUS pin 50 80 µA
BATTERY CHARGER FAST-CHARGE
VO(REG) Battery regulation voltage VBUS = 5.5 V, IOUT = 25 mA, (VTS_0C<VTS<VTS_45C) 4.16 4.20 4.23 V
VO_HT(REG) Battery hot regulation Voltage VBUS = 5.5 V, IOUT = 25 mA, (VTS_45C<VTS<VTS_60C) 4.02 4.06 4.1
IOUT Programmed output "fast charge" current range VO(REG) > BAT > VLOWV, VBUS = 5 V,
RISET = 469 to 7.5 kΩ		 50 800 mA
VDO(IN-OUT) Drop-Out, VBUS – BAT Adjust VBUS down until IOUT = 0.5 A, BAT = 4.15 V,
RISET = 675, TJ <100°C.		 250 400 mV
IOUT Output "fast charge" formula VO(REG) > BAT > VLOWV, VBUS = 5 V KISET/RISET A
KISET Fast charge current factor RISET = KISET /IOUT; 250 mA ≤ IOUT < 800 mA 373 390 407 AΩ
RISET = KISET /IOUT; 50mA ≤ ICHG < 250 mA 375 395 416
RISET = KISET /IOUT; 10 < ICHG < 50 mA 320 400 490
PRECHARGE – INTERNALLY SET
VLOWV Pre-charge to fast-charge transition threshold 2.4 2.5 2.6 V
tDGL1(LOWV) Deglitch time on pre-charge to fast-charge transition 100 μs
tDGL2(LOWV) Deglitch time on fast-charge to pre-charge transition 32 ms
IPRE-CHG Pre-charge current, Internally set BAT < VLOWV, ICHG ≥ 250 mA 18 20 22 % IOUT
TERMINATION – INTERNALLY SET
ITERM Termination current, Internally set ICHG ≥ 250 mA 8 10 12 % ICHG
tDGL(TERM) Deglitch time, termination detected 29 ms
RECHARGE OR REFRESH
VRCH Recharge detection threshold- normal temp VTS_0C<VTS<VTS_45C, BAT: 4.2 V → VRCH VO(REG)
–0.120		 VO(REG)
–0.095		 VO(REG)
–0.070		 V
Recharge detection threshold-hot temp VTS_45C<VTS<VTS_60C, BAT: 4.15 V → VRCH VO(REG)
–0.130		 VO(REG)
–0.105		 VO(REG)
–0.80		 V
tDGL1(RCH) Deglitch time, recharge threshold detected VTS_0C<VTS<VTS_45C, BAT: 4.25 V → 3.5 V in 1 µS ; tDGL(RCH) is time to ISET ramp 29 ms
tDGL2(RCH) Deglitch time, recharge threshold in BAT_Detect mode VTS_0C<VTS<VTS_45C, BAT: 3.5 V inserted;
tDGL(RCH) is time to ISET ramp		 3.6 ms
BATTERY DETECTION ROUTINE
VREG_BD BAT Reduced regulation during battery detect VTS_0C<VTS<VTS_45C, Battery present VO(REG)
–0.45		 VO(REG)
–0.4		 VO(REG)
–0.35		 V
VBD_SINK Sink current during VREG_BD VTS_0C<VTS<VTS_45C, Battery present 5 7 9 mA
tDGL1(HI/LOW_REG) Regulation time at VREG or VREG_BD VTS_0C<VTS<VTS_45C, Battery present 25 ms
VBD_HI High battery detection threshold VTS_0C<VTS<VTS_45C, Battery present VO(REG)
–0.158		 VO(REG)
–0.108		 VO(REG)
–0.058		 V
VBD_LO Low battery detection threshold VTS_0C<VTS<VTS_45C, Battery present VREG_BD
+0.05		 VREG_BD
+0.1		 VREG_BD
+0.15		 V
BATTERY CHARGING TIMERS AND FAULT TIMERS
tPRECHG Pre-charge safety timer value Restarts when entering Pre-charge; Always enabled when in pre-charge. VTS<VSM(TS) 1700 1940 2250 s
tMAXCH Charge safety timer value Clears fault or resets at UVLO, EN disable, BAT Short, exiting LOWV and Refresh 34000 38800 45000 s
tMAXTERM Termination timer in limited power charge mode Limited power charge mode, terminate charge when VIN DPM active, normal termination conditions met and this termer expires 6800 7760 9000 s
BATTERY-PACK NTC MONITOR
VTSB TS Bias Voltage IVTSB < 1 mA 2 2.2 2.4 V
IVTSB (Min) Maximum current from TS-bias pin (short circuit protection) 1 mA
CVTSB Optional capacitance for ESD 0.1 µF
CTS Optional capacitance for ESD 0.22 µF
V0C 57 %VTSB
V0C-Hyst Hysteresis on 0C comparator 1 %VTSB
V10C 46 %VTSB
V10C-Hyst Hysteresis on 10C comparator 1 %VTSB
V45C 18.6 %VTSB
V45C-Hyst Hysteresis on 45C comparator 1 %VTSB
V60C 12 %VTSB
V60C-Hyst Hysteresis on 60C comparator 1 %VTSB
tDGL(TS_10C) Deglitch for TS thresholds: 10C Normal to cold operation: VTS: 30% → 50% VTSB 50 ms
Cold to Normal operation: VTS: 50% → 30% VTSB 12
tDGL(TS) Deglitch for TS thresholds: 10/45/60C Battery charging 30 ms
VLP(TS) Limited power charge mode threshold - Enter VTS: 0.4VTSB → 0.9VTSB; 75 80 85 %VTSB
VHYS-LP(TS) Hysteresis exiting limited power charge mode VTS: 1.7 V → 0.5 V; 5
tDGL(LDO) Deglitch exit limited power charge mode between states Battery charging 57 ms
Deglitch enter limited power charge mode between states 8 µs
THERMAL REGULATION
TJ(REG) Temperature regulation limit 125 °C
TJ(OFF) Thermal shutdown temperature 155 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
LOGIC LEVELS ON EN
VIL Logic LOW input voltage Sink 8 µA 0.4 V
VIH Logic HIGH input voltage Source 8 µA 1.4 V
IIL Sink current required for LO 2 10.5 µA
IIH Source current required for HI 0.8 2 µA
LOGIC LEVELS ON CHG AND PG
VOL Output LOW voltage ISINK = 5 mA 0.4 V
ILEAK Leakage current into IC Vchg = 5 V, VPG = 5 V 1 µA
LOAD MODE (EN=LOW)
BAT_REV_ST Minimum voltage for load mode 2.8 3.0 3.2 V
VDO(BAT-VBUS) Drop-Out, V(BAT) – V(VBUS) Adjust VBUS down until I(VBUS) = 0.1 A,
BAT = 4.15 V, TJ <100°C.		 200 320 mV
VBUS-LM Load mode exiting threshold (VBUS above BAT) BAT = 3.6 V, VBUS: rising 3 V → 4 V –100 –50 0 mV
VHYS-VBUSLM Hysteresis on VBUS-LM falling BAT = 3.6 V, VBUS: 4 V → 3 V 150 mV
tDGL(LM_Exit) Deglitch time on exiting load mode 100 mS
tDGL(LM-Enter) Deglitch time on VHYS-VBUSLM same as entering load mode 5 µs
ILM_MIN The minimum load current to keep IC in load mode During load mode 0.3 1.8 3.1 mA
IREV_LIMIT Initial current limit in load mode for blanking time tREV_LIMIT_BLK BAT = 3.6 V 130 170 215 mA
tREV_LIMIT_BLK Blanking time for initial current limit 200 ms
IREV_LIMIT_BK Reverse load mode current limit after the initial blanking time 40 55 70 mA
tREV_LIMIT_REC Delay time to set load current limit back to IREV_LIMIT Reverse current drops from 100% to 30% of IREV_LIMIT_BK 200 ms

7.6 Typical Characteristics

tc2_lusa76.gifFigure 1. Tracking vs BAT
tc1_lusa76.gifFigure 2. Tracking vs Temperature