8.3.1 Dynamic Power Path Management

The bq24250C features a SYS output that powers the external system load connected to the battery. This output is active whenever a valid source is connected to IN or BAT. The following discusses the behavior of SYS with a source connected to the supply or a battery source only.

When a valid input source is connected to the input and the charge is enabled, the charge cycle is initiated. In case of VBAT > ~3.5V, the SYS output is connected to VBAT. If the SYS voltage falls to VMINSYS, it is regulated to the VSYSREG threshold to maintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge current into the battery. The current from the supply is shared between charging the battery and powering the system load at SYS.

The dynamic power path management (DPPM) circuitry of the bq24250C monitors the current limits continuously and if the SYS voltage falls to the VMINSYS voltage, it adjusts charge current to maintain the minimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the load increases further, the bq24250C enters battery supplement mode. During supplement mode, the battery FET is turned on and the battery supplements the system load.

If the battery is ever 5% above the regulation threshold, the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to safe operating levels. Battery OVP FAULT is shown in the I2C FAULT registers.

When no input source is available at the input and the battery is connected, the battery FET is turned on similar to supplement mode. The battery must be above VBATUVLO threshold to turn on the SYS output. In this mode, the current is not regulated;

8.3.2 Production Test Mode

To aid in end mobile device product manufacturing, the bq24250C includes a Production Test Mode (PTM), where the device is essentially a DC-DC buck converter. In this mode the input current limit to the charger is disabled and the output current limit is limited only by the inductor cycle-by-cycle current (e.g. 3.5A). The PTM mode can be used to test systems with high transient loads such as GSM transmission without the need of a battery being present.

As a means of safety, the Anyboot algorithm determines if a battery is not present at the output prior to enabling the PTM mode. If a battery is present and the software attempts to enter PTM mode, the device will not enable PTM mode.

8.3.3 AnyBoot Battery Detection

The bq24250C includes a sophisticated battery detection algorithm used to provide the system with the proper status of the battery connection. The AnyBoot battery algorithm also ensures the detection of voltage based battery protectors that may have a long closure time (due to the hysteresis of the protection switch and the cell capacity). The AnyBoot battery detection algorithm utilizes a dual-voltage based detection methodology where the system rail switches between two primary voltage levels. The period of the voltage level shift is 64ms and therefore the power supply rejection of the down-system electronics detects this shift as essentially DC.

The AnyBoot algorithm has essentially 3 states. The 1^st state is used to determine if the device has terminated with a battery attached. If it has terminated due to the battery not being present, then the algorithm moves to the 2^nd and 3^rd states. The 2^nd and 3^rd states shift the system voltage level between 4.2V and 3.72V. In each state there are comparator checks to determine if a battery has been inserted. The two states ensure the detection of a battery even if the voltage of the cell is at the same level of the comparator thresholds. The algorithm will remain in states 2 and 3 until a battery has been inserted. The flow diagram details for the Anyboot algorithm are shown in Figure 14.

Figure 14. AnyBoot Battery Detection Flow Diagram

8.4.1 Charge Profile

The bq24250C provides a switch-mode buck regulator with output power path and a charge controller to provide optimum performance over the full battery charge cycle. The control loop for the buck regulator has 7 primary feedback loops that can set the duty cycle:

1. Constant Current (CC)
2. Constant Voltage (CV)
3. Minimum System Voltage (MINSYS)
4. Input Current (I_ILIM)
5. Input Voltage (V_{IN_DPM})
6. Die Temperature
7. Cycle by Cycle Current

The feedback with the minimum duty cycle will be chosen as the active loop. The bq24250C supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path Management (DPPM) feature regulates the system voltage to a minimum of V_MINSYS, so that startup is enabled even with a missing or deeply discharged battery. This provides a much better overall user experience in mobile applications. The figure below illustrates a typical charge profile while also demonstrating the minimum system output voltage regulation.

Figure 15. Typical Charge Profile

Figure 16 demonstrates a measured charge profile with the bq24250C while charging a 2700mAh Li-Ion battery at a charge rate of 1A.

Figure 16. bq24250C Charge Profile while Charging a 2700 mAh Battery at a 1A Charge Rate

Figure 17 illustrates the precharge behavior of the above charge profile by narrowing the time axis to 0 – 120 seconds.

Figure 17. bq24250C Charge Profile While Charging a 2700-mAh Battery at a 1A Charge During Precharge

8.4.2 EN1/EN2 Pins

The bq24250C is I²C and Stand Alone part. The EN1 and EN2 pins are available in this IC spin to support USB 2.0 compliance. These pins are used for Input Current Limit Configuration I. Set EN1 and EN2 to control the maximum input current and enable USB compliance. See Table 1 below for programming details.

When the input current limit pins change state, the V_{IN_DPM} threshold changes as well. See Table 1 for the detailed truth table:

8.4.3 I²C Operation (Host Mode / Default Mode)

There are two primary modes of operation when interacting with the charge parameters of the bq24250C charger: 1) Host mode operation where the I²C registers set the charge parameters, and 2) Default mode where the register defaults set the charge parameters.

Figure 18 illustrates the behavior of the bq24250C when transitioning between host mode and stand alone mode:

Figure 18. Host Mode and Stand Alone Mode Handoff

Once the battery or input is inserted and above the good thresholds, the device determines if an I²C command has been received in order to discern whether to operate from the I²C registers or the internal register defaults. In stand-alone mode the input current limit is set by the EN1/EN2 pins. If the watch dog timer is enabled, the device will enter stand alone operation once the watchdog timer expires and re-initiate the default charge settings.

8.4.4 External Settings: ISET, ILIM and VIN_DPM

If the external resistor settings are used, the following equations can be followed to configure the charge settings.

The fast charge current resistor (R_ISET) can be set by using the following formula:

Equation 1.

Where I_FC is the desired fast charge current setting in Amperes.

The input current limit resistor (R_ILIM) can be set by using the following formula:

Equation 2.

Where I_IC is the desired input current limit in Amperes.

Based on the application diagram reference designators, the resistor R1 and R2 can be calculated as follows to set V_{IN_DPM}:

Equation 3.

V_{IN_DPM} should be chosen first along with R₁. Choosing R₁ first will ensure that R₂ will be greater than the resistance chosen. This is the case since V_{IN_DPM} should be chosen to be greater than 2x V_{REF_DPM}.

If external resistors are not desired in order to reduce the BOM count, the VDPM and the ILIM pins can be shorted to set the internal defaults. The ISET resistor cannot be shorted in order to avoid an unstable charging state.Note that floating the ILIM pin will result in zero charge current if the external ISET is configured via the I²C register. Table 2 summarizes the settings when the ILIM, ISET, and V_{IN_DPM} pins are shorted to GND:

8.4.5 Transient Response

The bq24250C includes an advanced hybrid switch mode control architecture. When the device is regulating the charge current (fast-charge), a traditional voltage mode control loop is used with a Type-3 compensation network. However, the bq24250C switches to a current mode control loop when the device enters voltage regulation. Voltage regulation occurs in three charging conditions: 1) Minimum system voltage regulation (battery below MINSYS), 2) Battery voltage regulation (I_BAT < I_CHG), and 3) Charge Done (V_SYS = V_BAT + 3.5%). This architecture allows for superior transient performance when regulating the voltage due to the simplification of the compensation when using current mode control. The below transient response plot illustrates a 0A to 2A load step with 4.7ms full cycle and 12% duty cycle. A 3.9V Li-Ion battery is used. The input voltage is set to 5V, charge current is set to 0.5A and the input current is limited to 0.5A. Note that a high line impedance input supply was used to indicate a realistic input scenario (adapter and cable). This is illustrated by the change in V_IN seen at the input of the IC.

Figure 19 shows a ringing at both the input voltage and the input current. This is caused by the input current limit speed up comparator.

Figure 19. 2A Load Step Transient

8.4.6 Input Voltage Based DPM

During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage deceases. Once the supply drops to VIN_DPM, the input current limit is reduced down to prevent the further drop of the supply. When the IC enters this mode, the charge current is lower than the set. This feature ensures IC compatibility with adapters with different current capabilities without a hardware change.

8.4.7 Sleep Mode

The bq24250C enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold, VBAT+VSLP, and VIN is higher than the under-voltage lockout threshold, VUVLO. This feature prevents draining the battery during the absence of VIN. When VIN < VBAT+VSLP, the bq24250C turns off the PWM converter, turns on the battery FET, sends a single 256µs pulse is sent on the STAT and INT outputs and the FAULT/STAT bits of the status registers are updated in the I²C. Once VIN > VBAT+VSLP with the hysteresis, the FAULT bits are cleared and the device initiates a new charge cycle.

8.4.8 Input Over-Voltage Protection

The bq24250C provides over-voltage protection on the input that protects downstream circuitry. The built-in input over-voltage protection to protect the device and other components against damage from overvoltage on the input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq24250C turns off the PWM converter, turns the battery FET, sends a single 256μs pulse is sent on the STAT and INT outputs and the FAULT/STAT bits of the status registers and the battery/supply status registers are updated in the I²C. Once the OVP fault is removed, the FAULT bits are cleared and the device returns to normal operation. The OVP threshold for the bq24250 is programmable from 6.5V to 10.5V using VOVP bits in register #7.

8.4.9 NTC Monitor

The bq24250C includes the integration of an NTC monitor pin that complies with a modified JEITA specification (PSE also available upon request). The voltage based NTC monitor allows for the use of any NTC resistor with the use of the circuit shown in Figure 20.

Figure 20. Voltage Based NTC circuit

The use of R3 is only necessary when the NTC does not have a beta near 3500K. When deviating from this beta, error will be introduced in the actual temperature trip thresholds. The trip thresholds are summarized below which are typical values provided in the specification table. Note that the T_WARM threshold is just a warning for the warm temperature, the device will generate an interrupt but it will not affect the charging process.

When sizing for R2 and R3, it is best to solve two simultaneous equations that ensure the temperature profile of the NTC network will cross the V_HOT and V_COLD thresholds. The accuracy of the V_WARM and V_COOL threshold will depend on the beta of the chosen NTC resistor. The two simultaneous equations are shown below:

Equation 4.

Where the NTC resistance at the V_HOT and V_COLD temperatures must be resolved as follows:

Equation 5.

To be JEITA compliant, T_COLD must be 0°C and T_HOT must be 60°C. If an NTC resistor is chosen such that the beta is 4000K and the nominal resistance is 10kΩ, the following R2 and R3 values result from the above equations:

R₂ = 5 kΩ

R₃ = 9.82 kΩ

Figure 21 illustrates the temperature profile of the NTC network with R2 and R3 set to the above values.

Figure 21. Voltage Based NTC Circuit Temperature Profile

Once the resistors are configured, the internal JEITA algorithm will apply the below profile at each trip point for battery voltage regulation and charge current regulation.

Figure 22. Modified JEITA Profile for Voltage and Current Regulation Loops

8.4.10 Safety Timer

At the beginning of charging process, the bq24250C starts the safety timer. This timer is active during the entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode where charging is disabled. The safety timer time is selectable using the I²C interface. A single 256μs pulse is sent on the STAT and INT outputs and the FAULT/ bits of the status registers are updated in the I²C. This function prevents continuous charging of a defective battery if the host fails to reset the safety timer. When 2xTMR_EN bit is set to “1”, the safety timer runs at a rate 2x slower than normal (the timer is extended) under the following conditions:

• Pre-charge or linear mode (minimum system voltage mode),
• During thermal regulation where the charge current is reduced,
• During TS fault where the  charge current is reduced

The safety timer is suspended during OVP, TS fault where charge is disabled, thermal shut down, and sleep mode.        

8.4.11 Watchdog Timer

In addition to the safety timer, the bq24250C contains a 50-second watchdog timer that monitors the host through the I²C interface. Once a write is performed on the I²C interface, a watchdog timer is reset and started. The watchdog timer can be disabled by writing “0” on WD_EN bit of register #1. Writing “1” on that bit enables it and reset the timer.

If the watchdog timer expires, the IC enters DEFAULT mode where the default charge parameters are loaded and charging continues. The I²C may be accessed again to re-initialize the desired values and restart the watchdog timer as long as the safety timer has not expired. Once the safety timer expires, charging is disabled.

8.4.12 Thermal Regulation and Thermal Shutdown

During the charging process, to prevent overheat of the chip, bq24250C monitors the junction temperature, T_J, of the die and begins to taper down the charge current once T_J reaches the thermal regulation threshold, TREG. The charge current is reduced when the junction temperature increases above TREG. Once the charge current is reduced, the system current is reduced while the battery supplements the load to supply the system. This may cause a thermal shutdown of the IC if the die temperature rises too. At any state, if T_J exceeds TSHTDWN, bq24250C suspends charging and disables the buck converter. During thermal shutdown mode, PWM is turned off, all safety timers are suspended, and a single 256μs pulse is sent on the STAT and INT outputs and the FAULT/STAT bits of the status registers are updated in the I²C. A new charging cycle begins when T_J falls below TSHTDWN by approximately 10°C.

8.4.13 Fault Modes

The bq24250C includes several hardware fault detections. This allows for specific conditions that could cause a safety concern to be detected. With this feature, the host can be alleviated from monitoring unsafe charging conditions and also allows for a “fail-safe” if the host is not present. The table below summarizes the faults that are detected and the resulting behavior.

8.4.14 Serial Interface Description

The bq24250C uses an I²C compatible interface to program charge parameters. I²C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor, see I²C-Bus Specification, Version 5, October 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

Thebq24250C device works as a slave and supports the following data transfer modes, as defined in the I²C Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps).  The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. The I²C circuitry is powered from IN when a supply is connected.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The bq24250C device only supports 7-bit addressing. The device 7-bit address is defined as ‘1101010’ (0x6Ah).

To avoid I²C hang-ups, a timer (t_I2CRESET) runs during I2C transactions. If the transaction takes longer than t_I2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START and repeated START conditions and stops when a valid STOP condition is sent.

8.4.14.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 23. All I²C -compatible devices should recognize a start condition.

Figure 23. START and STOP Condition

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 24). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

Figure 24. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in this section will result in 0xFFh being read out.

Figure 25. Acknowledge on the I2C Bus

Figure 26. Bus Protocol

Register #1
Memory location: 00, Reset state: x0xx xxxx

Register #2
Memory location: 01, Reset state: xxxx 1100

Register #3
Memory location: 02, Reset state: 1000 1111

Register #4
Memory location: 03, Reset state: 1111 1000

Register #5
Memory location: 04, Reset state: xx00 x010

Register #6
Memory location: 05, Reset state: 101x 1xxx

Register #7
Memory location: 06, Reset state: 1110 0000