Table 3. Design Parameters

9.2.2.1 Inductor Selection

The bq2461x has 600-kHz switching frequency to allow the use of small inductor and capacitor values. Inductor saturation current should be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

Equation 12.

The inductor ripple current depends on input voltage (V_IN), duty cycle (D = V_OUT/V_IN), switching frequency (f_S) and inductance (L):

Equation 13.

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9 V to 12.6 V for a three-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives the maximum inductor ripple current. Another example is a four-cell battery, where the battery voltage range is from 12 V to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of 20% to 40% of maximum charging current as a trade-off between inductor size and efficiency for a practical design.

The bq24618 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charge current-sensing resistor to prevent negative inductor current. The typical UCP threshold is 5 mV falling edge, corresponding to 0.5 A falling edge for a 10-mΩ charge current-sensing resistor.

9.2.2.2 Input Capacitor

The input capacitor should have enough ripple current rating to absorb the input switching ripple current. The worst-case RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst-case capacitor RMS current I_CIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation:

Equation 14.

A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V rating or higher capacitor is preferred for 20-V input voltage. A 10-µF to 20-µF capacitor is suggested for typical 3-A to 4-A charging current.

9.2.2.3 Output Capacitor

The output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current I_COUT is given:

Equation 15.

The output capacitor voltage ripple can be calculated as follows:

Equation 16.

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC.

The bq24618 has an internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed from 12 kHz to 17 kHz. The preferred ceramic capacitor is 25-V or higher rating, X7R or X5R for 4-cell applications.

9.2.2.4 Power MOSFET Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6 V of gate drive voltage. MOSFETs of 30-V or higher voltage rating are preferred for 20-V input voltage and 40-V or higher rating MOSFETs are preferred for 20-V to 28-V input voltage.

Figure-of-merit (FOM) is usually used for selecting proper the MOSFET, based on a trade-off between the conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of a MOSFET ON-resistance, r_DS(on), and the gate-to-drain charge, Q_GD. For a bottom-side MOSFET, FOM is defined as the product of the MOSFET ON-resistance, r_DS(on), and the total gate charge, Q_G.

Equation 17.

The lower the FOM value, the lower the total power loss. Usually, lower r_DS(on) has higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D = V_OUT/V_IN), charging current (I_CHG), MOSFET ON-resistance r_DS(on)), input voltage (V_IN), switching frequency (f_S), turnon time (t_on) and turnoff time (t_off):

Equation 18.

The first item represents the conduction loss. Usually MOSFET r_DS(on) increases by 50% with a 100ºC junction temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are given by:

Equation 19.

where

• Q_sw is the switching charge.
• I_on is the turnon gate-drive current.
• I_off is the turnoff gate-drive current.

If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (Q_GD) and gate-to-source charge (Q_GS):

Equation 20.

Total gate drive current can be estimated by the REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turnon gate resistance (R_on), and turnoff gate resistance (R_off) of the gate driver:

Equation 21.

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode:

Equation 22.

If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the switching cycle to prevent negative inductor current.

As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum charging current in nonsynchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging current sensing resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum nonsynchronous mode charging current.

MOSFET gate driver power loss contributes to the dominant losses on the controller IC when the buck converter is switching. Choosing a MOSFET with a small Q_{g_total} reduces the IC power loss to avoid thermal shutdown.

Equation 23.

where

• Q_{g_total} is the total gate charge for both upper and lower MOSFET at 6 V V_REGN.

9.2.2.5 Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second-order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin. The ACP/ACN pin must be placed after the input ACFET in order to avoid overvoltage stress on these pins during hot plug-in.

There are several methods to damping or limiting the overvoltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the overvoltage level to an IC-safe level. However, these two solutions may not have low cost or small size.

A cost-effective and small-size solution is shown in Figure 20. R1 and C1 comprise a damping RC network to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for reverse voltage protection for the VCC pin (it can be the body diode of the input ACFET). C2 is a VCC pin decoupling capacitor, and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping RC network to further protect the IC from high dv/dt and high-voltage spikes. The value of C2 should be less than the value of C1 so R1 can be dominant over the ESR orf C1 to get enough damping effect for hot plug-in. The R1 and R2 packages must be sized to handle the inrush current power loss according to the resistor manufacturer’s data sheet. The filter component values always must be verified with the real application, and minor adjustments may be needed to fit in the real application circuit.

Figure 20. Input Filter

9.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines

The bq24618 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant frequency, f_o, is approximately 12 kHz to 17 kHz for the bq24618.

The following table provides a summary of typical LC components for various charge currents:

9.2.2.7 Component List for Typical System Circuit of Figure 19