JAJSBJ1B July   2010  – January 2020 BQ24650

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Battery Voltage Regulation
      2. 8.3.2  Input Voltage Regulation
      3. 8.3.3  Battery Current Regulation
      4. 8.3.4  Battery Precharge
      5. 8.3.5  Charge Termination and Recharge
      6. 8.3.6  Power Up
      7. 8.3.7  Enable and Disable Charging
      8. 8.3.8  Automatic Internal Soft-Start Charger Current
      9. 8.3.9  Converter Operation
      10. 8.3.10 Synchronous and Non-Synchronous Operation
      11. 8.3.11 Cycle-by-Cycle Charge Undercurrent
      12. 8.3.12 Input Overvoltage Protection (ACOV)
      13. 8.3.13 Input Undervoltage Lockout (UVLO)
      14. 8.3.14 Battery Overvoltage Protection
      15. 8.3.15 Cycle-by-Cycle Charge Overcurrent Protection
      16. 8.3.16 Thermal Shutdown Protection
      17. 8.3.17 Temperature Qualification
      18. 8.3.18 Charge Enable
      19. 8.3.19 Inductor, Capacitor, and Sense Resistor Selection Guidelines
      20. 8.3.20 Charge Status Outputs
      21. 8.3.21 Battery Detection
        1. 8.3.21.1 Example
    4. 8.4 Device Functional Modes
      1. 8.4.1 Converter Operation
      2. 8.4.2 Synchronous and Non-Synchronous Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Power MOSFETs Selection
        5. 9.2.2.5 Input Filter Design
        6. 9.2.2.6 MPPT Temperature Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

5 V ≤ VVCC ≤ 28 V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VVCC_OP VCC input voltage operating range 5 28 V
QUIESCENT CURRENTS
IBAT Total battery discharge current (sum of currents into VCC, BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V VCC < VBAT, VCC > VUVLO (SLEEP) 15 µA
Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V VCC > VBAT, VCC > VUVLO, CE = LOW 5 µA
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charge done		 5 µA
IAC Adapter supply current (sum of current into VCC pin) VCC > VBAT, VCC > VUVLO, CE = LOW 0.7 1 mA
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, charge done		 2 3 mA
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 10 nC [1]		 25 mA
CHARGE VOLTAGE REGULATION
VREG Feedback regulation voltage 2.1 V
Charge voltage regulation accuracy TJ = 0°C to 85°C –0.5% 0.5%
TJ = –40°C to 125°C –0.7% 0.7%
IVFB Leakage current into VFB pin VFB = 2.1 V 100 nA
CURRENT REGULATION – FAST CHARGE
VIREG_CHG SRP-SRN current sense voltage range VIREG_CHG = VSRP – VSRN 40 mV
Charge current regulation accuracy VIREG_CHG = 40 mV –3% 3%
CURRENT REGULATION – PRE-CHARGE
VPRECHG Precharge current sense voltage range VIREG_PRCHG = VSRP – VSRN 4 mV
Precharge current regulation accuracy VIREG_PRECH = 4 mV –25% 25%
CHARGE TERMINATION
VTERMCHG Termination current sense voltage range VITERM = VSRP – VSRN 4 mV
Termination current accuracy VITERM = 4 mV –25% 25%
Deglitch time for termination (both edges) 100 ms
tQUAL Termination qualification time VBAT > VRECH and ICHG < ITERM 250 ms
IQUAL Termination qualification current Discharge current once termination is detected 2 mA
INPUT VOLTAGE REGULATION
VMPPSET MPPSET regulation voltage 1.2 V
Input voltage regulation accuracy –0.6% 0.6%
IMPPSET Leakage current into MPPSET pin VMPPSET = 7 V, TA = 0 – 85°C 1 µA
VMPPSET_CD MPPSET shorted to disable charge 75 mV
VMPPSET_CE MPPSET released to enable charge 175 mV
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO AC undervoltage rising threshold Measure on VCC 3.65 3.85 4 V
VUVLO_HYS AC undervoltage hysteresis, falling 350 mV
VCC LOWV COMPARATOR
VVCC LOWV_fall Falling threshold, disable charge Measure on VCC 4.1 V
VVCC LOWV_rise Rising threshold, resume charge 4.35 V
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP _FALL SLEEP falling threshold VVCC – VSRN to enter SLEEP 40 100 150 mV
VSLEEP_HYS SLEEP hysteresis 500 mV
SLEEP rising shutdown deglitch VCC falling below SRN 100 ms
SLEEP falling powerup deglitch VCC rising above SRN, Delay to exit SLEEP mode 30 ms
BAT LOWV COMPARATOR
VLOWV Precharge to fast charge transition (LOWV threshold) Measure on VFB pin 1.54 1.55 1.56 V
VLOWV_HYS LOWV hysteresis 100 mV
LOWV rising deglitch VFB falling below VLOWV 25 ms
LOWV falling deglitch VFB rising above VLOWV + VLOWV_HYS 25 ms
RECHARGE COMPARATOR
VRECHG Recharge threshold (with respect to VREG) Measure on VFB pin 35 50 65 mV
Recharge rising deglitch VFB decreasing below VRECHG 10 ms
Recharge falling deglitch VFB increasing above VRECHG 10 ms
BAT OVERVOLTAGE COMPARATOR
VOV_RISE Overvoltage rising threshold As percentage of VFB 104%
VOV_FALL Overvoltage falling threshold As percentage of VFB 102%
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV AC overvoltage rising threshold on VCC 31 32 33 V
VACOV_HYS AC overvoltage falling hysteresis 1 V
AC overvoltage deglitch (both edges) Delay to changing the STAT pins 1 ms
AC overvoltage rising deglitch Delay to disable charge 1 ms
AC overvoltage falling deglitch Delay to resume charge 20 ms
THERMAL SHUTDOWN COMPARATOR
TSHUT Thermal shutdown rising temperature Temperature increasing 145 °C
TSHUT_HYS Thermal shutdown hysteresis 15 °C
Thermal shutdown rising deglitch Temperature increasing 100 µs
Thermal shutdown falling deglitch Temperature decreasing 10 ms
THERMISTOR COMPARATOR
VLTF Cold temperature rising threshold As percentage to VVREF 72.5% 73.5% 74.5%
VLTF_HYS Rising hysteresis 0.2% 0.4% 0.6%
VHTF Hot temperature rising threshold 46.7% 47.5% 48.3%
VTCO Cut-off temperature rising threshold 44.3% 45% 45.7%
Deglitch time for temperature out of range detection VTS < VLTF, or VTS < VTCO, or
VTS < VHTF 		400 ms
Deglitch time for temperature in valid range detection VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF 20 ms
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VOC Charge overcurrent rising threshold Current rising, in synchronous mode measure (VSRP – VSRN) 80 mV
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET Charge undercurrent falling threshold Switch from CCM to DCM, VSRP > 2.2V 1 5 9 mV
BATTERY-SHORTED COMPARATOR (BATSHORT)
VBATSHT BAT short falling threshold, forced non-synchronous mode VSRP falling 2 V
VBATSHT_HYS BAT short rising hysteresis 200 mV
tBATSHT_DEG Deglitch on both edges 1 µs
LOW CHARGE CURRENT COMPARATOR
VLC Low charge current falling threshold Measure V(SRP-SRN) 1.25 mV
VLC_HYS Low charge current rising hysteresis 1.25 mV
tLC_DEG Deglitch on both edges 1 µs
VREF REGULATOR
VVREF_REG VREF regulator voltage VVCC > VUVLO, 0 – 35 mA load 3.267 3.3 3.333 V
IVREF_LIM VREF current limit VVREF = 0 V, VVCC > VUVLO 35 mA
REGN REGULATOR
VREGN_REG REGN regulator voltage VVCC > 10 V, MPPSET > 175 mV 5.7 6.0 6.3 V
IREGN_LIM REGN current limit VREGN = 0 V, VVCC > VUVLO, MPPSET < 75 mV 40 mA
BATTERY DETECTION
tWAKE Wake timer Max time charge is enabled 500 ms
IWAKE Wake current RSENSE = 10 mΩ 50 125 200 mA
tDISCHARGE Discharge timer Max time discharge current is applied 1 sec
IDISCHARGE Discharge current 6 mA
IFAULT Fault current after a timeout fault 2 mA
IQUAL Termination qualification current 2 mA
tQUAL Termination qualification time 250 ms
VWAKE Wake threshold (with respect to VREG) Voltage on VFB to detect battery absent during wake 50 mV
VDISCH Discharge threshold Voltage on VFB to detect battery absent during discharge 1.55 V
PWM HIGH-SIDE DRIVER (HIDRV)
RDS_HI_ON High-side driver (HSD) turnon resistance VBTST – VPH = 5.5 V 3.3 6 Ω
RDS_HI_OFF High-side driver turnoff resistance 1 1.4 Ω
VBTST_REFRESH Bootstrap refresh comparator threshold Voltage VBTST – VPH when low side refresh pulse is requested 4.0 4.2 V
PWM LOW-SIDE DRIVER (LODRV)
RDS_LO_ON Low-side driver (LSD) turn-on resistance 4.1 7 Ω
RDS_LO_OFF Low-side driver turn-off resistance 1 1.4 Ω
PWM DRIVERS TIMING
Driver dead-time Dead time when switching between LSD and HSD, No load at LSD and HSD 30 ns
PWM OSCILLATOR
VRAMP_HEIGHT PWM ramp height As percentage of VCC 7%
PWM switching frequency 510 600 690 kHz
INTERNAL SOFT START (8 STEPS TO REGULATION CURRENT ICHG)
Soft-start steps 8 step
Soft-start step time 1.6 ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up Delay from MPPSET > 175 mV to charger is allowed to turn on 1.5 s
LOGIC IO PIN CHARACTERISTICS (STAT1, STAT2, TERM_EN)
VOUT_LOW STAT1, STAT2 output low saturation voltage Sink current = 5 mA 0.5 V
IOUT_HI Leakage current V = 32 V 1.2 µA
VIN_LOW TERM_EN input low threshold voltage 0.4 V
VIN_HI TERM_EN input high threshold voltage 1.6 V
IIN_BIAS TERM_EN bias current VTERM_EN = 0.5 V 60 µA