JAJSBJ1B July 2010 – January 2020 BQ24650
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VCC | P | IC power positive supply. Place a 1-μF ceramic capacitor from VCC to GND and place it as close as possible to IC. Place a 10-Ω resistor from input side to VCC pin to filter the noise. |
2 | MPPSET | I | Input voltage set point. Use a voltage divider from input source to GND to set voltage on MPPSET to 1.2 V. To disable charge, pull MPPSET below 75 mV. |
3 | STAT1 | O | Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED with 10 kΩ to the pullup rail. LOW or LED light up indicates charge in progress. Otherwise stays HI or LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off. |
4 | TS | I | Temperature qualification voltage input. Connect to a negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. A 103AT-2 thermister is recommended. |
5 | STAT2 | O | Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED with 10 kΩ to the pullup rail. LOW or LED light up indicates charge is complete. Otherwise, stays HI or LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off. |
6 | VREF | P | 3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming voltage on TS and the pullup rail of STAT1 and STAT2. |
7 | TERM_EN | I | Charge termination enable. Pull TERM_EN to GND to disable charge termination. Pull TERM_EN to VREF to allow charge termination. TERM_EN must be terminated and cannot be left floating. |
8 | VFB | I | Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the battery terminals to this node to adjust the output battery voltage regulation. |
9 | SRN | I | Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN to GND for common-mode filtering. |
10 | SRP | P/I | Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP to GND for common-mode filtering. |
11 | GND | P | Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input and output capacitors of the charger. Only connect to GND through the thermal pad underneath the IC. |
12 | REGN | P | PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to GND, close to the IC. Use to drive low-side driver and high-side driver bootstrap Schottky diode from REGN to BTST. |
13 | LODRV | O | PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short trace. |
14 | PH | P | Switching node, charge current output inductor connection. Connect the 0.1-μF bootstrap capacitor from PH to BTST. |
15 | HIDRV | O | PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short trace. |
16 | BTST | P | PWM high-side driver positive supply. Connect the 0.1-µF bootstrap capacitor from PH to BTST. |
— | Thermal Pad | — | Exposed pad beneath the IC. The thermal pad must always be soldered to the board and have the vias on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate heat. |