8.2.2.1 Negative Output Voltage Protection

Reversely insert the battery pack into the charger output during production or hard shorts on battery to ground will generate negative output voltage on SRP, SRN, and BATSRC pins. IC internal electrostatic-discharge (ESD) diodes from GND pin to SRP or SRN pins and two anti-parallel (AP) diodes between SRP and SRN pins can be forward biased and negative current can pass through the ESD diodes and AP diodes when output has negative voltage. Small resistors for SRP, SRN and BATSRC (R12-R14) further limits the negative current into these pins. Suggest resistor value is 10 Ω for SRP, SRN, and BATSRC pins.

8.2.2.2 Reverse Input Voltage Protection

Q6, R12, and R13 in Figure 17 give system and IC protection from reversed adapter voltage. In normal operation, Q6 is turned off by negative Vgs. When adapter voltage is reversed, Q6 Vgs is positive. As a result, Q6 turns on to short gate and source of Q2 so that Q2 is off. Q2 body diode blocks negative voltage to system. However, CMSRC and ACDRV pins need R3 and R4 to limit the current due to the ESD diode of these pins when turned on. Q6 must has low Vgs threshold voltage and low Qgs gate charge so it turns on before Q2 turns on. R3 and R4 must have enough power rating for the power dissipation when the ESD diode is on. If Q1 is replaced by Schottky diode for reverse adapter voltage protection, no extra small MOSFET and resistors are needed.

Figure 17. Reverse Input Voltage Protection Circuit

8.2.2.3 Reduce Battery Quiescent Current

When the adapter is not present, if VCC is powered with voltage higher than UVLO directly or indirectly (such as through a LDO or switching converter) from battery, the internal BATFET charge pump gives the BATFET pin 6-V higher voltage than the SRN pin to drive the n-channel BATFET. As a result, the battery has higher quiescent current. This is only necessary when the battery powers the system due to a high system current that goes through the MOSFET channel instead of the body diode to reduce conduction loss and extend the battery working life. When the system is totally shutdown, it is not necessary to let the internal BATFET charge pump work. The host controller can turn off the switches in the battery pack to disconnect the battery from the system. Some packs may wake up again if the voltage on SRN pin stays above pack UVLO too long. By setting ChargeOption0() bit[1] to 1, host can enable current source inside charger IC to discharge the SRN pin quickly. As a result, the system is discharged down to zero to minimize the quiescent current.

8.2.2.4 Inductor Selection

The bq24780S has three selectable fixed switching frequency. Higher switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

Equation 6.

The inductor ripple current depends on input voltage (V_IN), duty cycle (D = V_OUT/V_IN), switching frequency (f_S) and inductance (L):

Equation 7.

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to 16.8V, and 12V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design.

The bq24780S has charge under current protection (UCP) by monitoring charging current sensing resistor cycle-by-cycle. The typical cycle-by-cycle UCP threshold is 5mV falling edge corresponding to 0.5A falling edge for a 10mΩ charging current sensing resistor. When the average charging current is less than 125mA for a 10mΩ charging current sensing resistor, the low side MOSFET is off until BTST capacitor voltage needs to refresh the charge. As a result, the converter relies on low side MOSFET body diode for the inductor freewheeling current.

8.2.2.5 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 8:

Equation 8.

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 19-20V input voltage. 10-20μF capacitance is suggested for typical of 3-4A charging current.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.

8.2.2.6 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current is given:

Equation 9.

The bq24780S has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25V X7R or X5R for output capacitor. 10-20μF capacitance is suggested for a typical of 3-4A charging current. Place the capacitors after charging current sensing resistor to get the best charge current regulation accuracy.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.

8.2.2.7 Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are preferred for 19-20V input voltage.

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, R_DS(ON), and the gate-to-drain charge, Q_GD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON) has higher cost with the same package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-resistance (R_DS(ON)), input voltage (V_IN), switching frequency (f_S), turn on time (t_on) and turn off time (t_off):

Equation 11.

The first item represents the conduction loss. Usually MOSFET R_DS(ON) increases by 50% with 100°C junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are given by:

Equation 12.

where Q_sw is the switching charge, I_on is the turn-on gate driving current and I_off is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (Q_GD) and gate-to-source charge (Q_GS):

Equation 13.

Gate driving current can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turn-on gate resistance (R_on) and turn-off gate resistance (R_off) of the gate driver:

Equation 14.

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode:

When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss depends on its forward voltage drop (V_F), non-synchronous mode charging current (I_NONSYNC), and duty cycle (D).

The maximum charging current in non-synchronous mode can be up to 0.25A for a 10mΩ charging current sensing resistor or 0.5A if battery voltage is below 2.5V. The minimum duty cycle happens at lowest battery voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.

8.2.2.8 Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The input filter must be carefully designed and tested to prevent over voltage event on VCC pin.

There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level. However these two solutions may not have low cost or small size.

A cost effective and small size solution is shown in Figure 18. The R1 and C1 are composed of a damping RC network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to VCC pin as close as possible. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when adapter hot plug-in. R2 and C2 should have 10us time constant to limit the dv/dt on VCC pin to reduce inrush current when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle inrush current power loss according to resistor manufacturer’s data sheet. The filter components value always need to be verified with real application and minor adjustments may need to fit in the real application circuit.

Figure 18. Input Filter