JAJSD88A May   2017  – January 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Ship Mode
        1. 9.3.1.1 Ship Mode Entry and Exit
      2. 9.3.2  High Impedance Mode
      3. 9.3.3  Active Battery Only Connected
      4. 9.3.4  Voltage Based Battery Monitor
      5. 9.3.5  Sleep Mode
      6. 9.3.6  Input Voltage Based Dynamic Power Management (VIN(DPM))
      7. 9.3.7  Input Overvoltage Protection and Undervoltage Status Indication
      8. 9.3.8  Battery Charging Process and Charge Profile
      9. 9.3.9  Dynamic Power Path Management Mode
      10. 9.3.10 Battery Supplement Mode
      11. 9.3.11 Default Mode
      12. 9.3.12 Termination and Pre-Charge Current Programming by External Components (IPRETERM)
      13. 9.3.13 Input Current Limit Programming by External Components (ILIM)
      14. 9.3.14 Charge Current Programming by External Components (ISET)
      15. 9.3.15 Safety Timer and Watchdog Timer
      16. 9.3.16 External NTC Monitoring (TS)
      17. 9.3.17 Thermal Protection
      18. 9.3.18 Typical Application Power Dissipation
      19. 9.3.19 Status Indicators (PG and INT)
      20. 9.3.20 Chip Disable (CD)
      21. 9.3.21 Buck (PWM) Output
      22. 9.3.22 Load Switch / LDO Output and Control
      23. 9.3.23 Manual Reset Timer and Reset Output (MR and RESET)
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1  Status and Ship Mode Control Register
        1. Table 12. Status and Ship Mode Control Register
      2. 9.6.2  Faults and Faults Mask Register
        1. Table 13. Faults and Faults Mask Register
      3. 9.6.3  TS Control and Faults Masks Register
        1. Table 14. TS Control and Faults Masks Register, Memory Location 0010
      4. 9.6.4  Fast Charge Control Register
        1. Table 15. Fast Charge Control Register
      5. 9.6.5  Termination/Pre-Charge and I2C Address Register
        1. Table 16. Termination/Pre-Charge and I2C Address Register
      6. 9.6.6  Battery Voltage Control Register
        1. Table 17. Battery Voltage Control Register
      7. 9.6.7  SYS VOUT Control Register
        1. Table 18. SYS VOUT Control Register
      8. 9.6.8  Load Switch and LDO Control Register
        1. Table 20. Load Switch and LDO Control Register
      9. 9.6.9  Push-button Control Register
        1. Table 21. Push-button Control Register
      10. 9.6.10 ILIM and Battery UVLO Control Register
        1. Table 22. ILIM and Battery UVLO Control Register, Memory Location 1001
      11. 9.6.11 Voltage Based Battery Monitor Register
        1. Table 23. Voltage Based Battery Monitor Register, Memory Location 1010
      12. 9.6.12 VIN_DPM and Timers Register
        1. Table 24. VIN_DPM and Timers Register
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Default Settings
        2. 10.2.2.2 Choose the Correct Inductance and Capacitance
        3. 10.2.2.3 Calculations
          1. 10.2.2.3.1 Program the Fast Charge Current (ISET)
          2. 10.2.2.3.2 Program the Input Current Limit (ILIM)
          3. 10.2.2.3.3 Program the Pre-charge/termination Threshold (IPRETERM)
          4. 10.2.2.3.4 TS Resistors (TS)
      3. 10.2.3 Application Performance Curves
        1. 10.2.3.1 Charger Curves
        2. 10.2.3.2 SYS Output Curves
        3. 10.2.3.3 Load Switch and LDO Curves
        4. 10.2.3.4 LS/LDO Output Curves
        5. 10.2.3.5 Timing Waveforms Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 商標
    3. 13.3 静電気放電に関する注意事項
    4. 13.4 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

YFP Package
25-Pin DSBGA
Top View
bq25120A po_slusbz9.gif

Pin Functions

PINI/ODESCRIPTION
NAMENO.
IN A2 I DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at least 1 µF of capacitance using a ceramic capacitor.
PMID A3, B3 I/O High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias derating from PMID to GND as close to the PMID and GND pins as possible. When entering Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.
GND A1, D5 Ground connection. Connect to the ground plane of the circuit.
PGND A5 Power ground connection. Connect to the ground plane of the circuit. Connect the output filter cap from the buck converter to this ground as shown in the layout example.
CD E2 I Chip Disable. Drive CD low to place the part in High-Z mode with battery only present, or enable charging when VIN is valid. Drive CD high for Active Battery mode when battery only is present, and disable charge when VIN is present. CD is pulled low internally with 900 kΩ.
SDA E4 I/O I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
SCL E5 I I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
ILIM C2 I Adjustable Input Current Limit Programming. Connect a resistor from ILIM to GND to program the input current limit. The input current includes the system load and the battery charge current. Connect ILIM to GND to set the input current limit to the internal default threshold. ILIM can also be updated through I2C.
LSCTRL E3 I Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to disable the LS/LDO output.
ISET C1 I Fast-Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast-charge current level. Connect a resistor from ISET to GND to set the charge current to the internal default. ISET can also be updated through I2C. While charging, the voltage at ISET reflects the actual charging current and can be used to monitor charge current if an ISET resistor is present and the device is not in host mode.
IPRETERM D1 I Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to GND to program the termination current between 5% and 20% of the charge current. The pre-charge current is the same as the termination current setting. Connect IPRETERM to GND to set the termination current to the internal default threshold. IPRETERM can also be updated through I2C.
INT D2 O Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during charging. INT is high impedance when charging is complete, disabled, or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT bit in the control register. Connect INT to a logic rail using an LED for visual indication of charge status or through a 100kΩ resistor to communicate with the host processor.
PG D4 O Open-drain Power Good status indication output. PG pulls to GND when VIN is above V(BAT) + VSLP and less that VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor, or use with an LED for visual indication. PG can also be configured as a push-button voltage shifted output (MRS) in the registers, where the output of the PG pin reflects the status of the MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.
RESET D3 O Reset Output. RESET is an open drain active low output that goes low when MR is held low for longer than tRESET, which is configurable by the MRRESET registers. RESET is deasserted after the tRESET_D, typically 400ms.
MR E1 I Manual Reset Input. MR is a push-button input that must be held low for greater than tRESET to assert the reset output. If MR is pressed for a shorter period, there are two programmable timer events, tWAKE1 and tWAKE2, that trigger an interrupt to the host. The MR input can also be used to bring the device out of Ship mode.
SW A4 O Inductor Connection. Connect to the switched side of the external inductor.
SYS B5 I System Voltage Sense Connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.
LS/LDO C5 O Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to assure stability. Be sure to account for capacitance bias voltage derating when selecting the capacitor.
VINLS B4, C4 I Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from this pin to GND.
BAT B1, B2 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 µF of ceramic capacitance.
TS C3 I Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to GND. The NTC is connected from TS to GND. The TS function provides four thresholds for JEITA compatibility. TS faults are reported by the I2C interface during charge mode.