JAJSD88A
May 2017 – January 2018
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
概略回路図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Ship Mode
9.3.1.1
Ship Mode Entry and Exit
9.3.2
High Impedance Mode
9.3.3
Active Battery Only Connected
9.3.4
Voltage Based Battery Monitor
9.3.5
Sleep Mode
9.3.6
Input Voltage Based Dynamic Power Management (VIN(DPM))
9.3.7
Input Overvoltage Protection and Undervoltage Status Indication
9.3.8
Battery Charging Process and Charge Profile
9.3.9
Dynamic Power Path Management Mode
9.3.10
Battery Supplement Mode
9.3.11
Default Mode
9.3.12
Termination and Pre-Charge Current Programming by External Components (IPRETERM)
9.3.13
Input Current Limit Programming by External Components (ILIM)
9.3.14
Charge Current Programming by External Components (ISET)
9.3.15
Safety Timer and Watchdog Timer
9.3.16
External NTC Monitoring (TS)
9.3.17
Thermal Protection
9.3.18
Typical Application Power Dissipation
9.3.19
Status Indicators (PG and INT)
9.3.20
Chip Disable (CD)
9.3.21
Buck (PWM) Output
9.3.22
Load Switch / LDO Output and Control
9.3.23
Manual Reset Timer and Reset Output (MR and RESET)
9.4
Device Functional Modes
9.5
Programming
9.5.1
Serial Interface Description
9.5.2
F/S Mode Protocol
9.6
Register Maps
9.6.1
Status and Ship Mode Control Register
Table 12.
Status and Ship Mode Control Register
9.6.2
Faults and Faults Mask Register
Table 13.
Faults and Faults Mask Register
9.6.3
TS Control and Faults Masks Register
Table 14.
TS Control and Faults Masks Register, Memory Location 0010
9.6.4
Fast Charge Control Register
Table 15.
Fast Charge Control Register
9.6.5
Termination/Pre-Charge and I2C Address Register
Table 16.
Termination/Pre-Charge and I2C Address Register
9.6.6
Battery Voltage Control Register
Table 17.
Battery Voltage Control Register
9.6.7
SYS VOUT Control Register
Table 18.
SYS VOUT Control Register
9.6.8
Load Switch and LDO Control Register
Table 20.
Load Switch and LDO Control Register
9.6.9
Push-button Control Register
Table 21.
Push-button Control Register
9.6.10
ILIM and Battery UVLO Control Register
Table 22.
ILIM and Battery UVLO Control Register, Memory Location 1001
9.6.11
Voltage Based Battery Monitor Register
Table 23.
Voltage Based Battery Monitor Register, Memory Location 1010
9.6.12
VIN_DPM and Timers Register
Table 24.
VIN_DPM and Timers Register
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Default Settings
10.2.2.2
Choose the Correct Inductance and Capacitance
10.2.2.3
Calculations
10.2.2.3.1
Program the Fast Charge Current (ISET)
10.2.2.3.2
Program the Input Current Limit (ILIM)
10.2.2.3.3
Program the Pre-charge/termination Threshold (IPRETERM)
10.2.2.3.4
TS Resistors (TS)
10.2.3
Application Performance Curves
10.2.3.1
Charger Curves
10.2.3.2
SYS Output Curves
10.2.3.3
Load Switch and LDO Curves
10.2.3.4
LS/LDO Output Curves
10.2.3.5
Timing Waveforms Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
デバイス・サポート
13.1.1
デベロッパー・ネットワークの製品に関する免責事項
13.2
商標
13.3
静電気放電に関する注意事項
13.4
Glossary
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
YFP|25
MXBG084M
サーマルパッド・メカニカル・データ
発注情報
jajsd88a_oa
jajsd88a_pm
10.2.3.4
LS/LDO Output Curves
Figure 93.
Startup Showing SS on LS/LDO in LDO Mode
Figure 94.
Short Circuit and Recovery for LDO