SLUSD33A November 2017 – January 2021 BQ25122
PRODUCTION DATA
Memory location 0x02h, Reset State: 1xxx 1000
7 (MSB) | 6 | 5 | 4 | 3 | 2 | 1 | 0 (LSB) |
1 | x | x | x | 1 | 0 | 0 | 0 |
R/W | R | R | R | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
B7 (MSB) | TS_EN | R/W | 1 | 0 – TS function disabled 1 – TS function enabled |
B6 | TS_FAULT1 | R | x | TS Fault mode: 00 – Normal, No TS fault 01 – TS temp < TCOLD or TS temp > THOT (Charging suspended) 10 – TCOOL > TS temp > TCOLD (Charging current reduced by half) 11 – TWARM < TS temp < THOT (Charging voltage reduced by 140 mV) |
B5 | TS_FAULT0 | R | x | |
B4 | Reserved | R | x | Reserved |
B3 | EN_INT | R/W | 1 | 0 – Disable INT function (INT only shows faults and does not show charge status) 1 – Enable INT function (INT shows faults and charge status) |
B2 | WAKE_M | R/W | 0 | 1 – Mask interrupt from Wake Condition from MR |
B1 | RESET_M | R/W | 0 | 1 – Mask RESET interrupt from MR . The RESET output is not masked by this bit. |
B0 (LSB) | TIMER_M | R/W | 0 | 1 – Mask Timer fault interrupt (safety) |