JAJSGQ2F August   2013  – March 2019

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      充電器の効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Power Point Tracking
      2. 7.3.2 Battery Undervoltage Protection
      3. 7.3.3 Battery Overvoltage Protection
      4. 7.3.4 Battery Voltage in Operating Range (VBAT_OK Output)
      5. 7.3.5 Push-Pull Multiplexer Drivers
      6. 7.3.6 Nano-Power Management and Efficiency
    4. 7.4 Device Functional Modes
      1. 7.4.1 Main Boost Charger Disabled (Ship Mode) - (VSTOR > VSTOR_CHGEN and EN = HIGH)
      2. 7.4.2 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS))
      3. 7.4.3 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN, VIN_DC > VIN(DC) and EN = LOW )
      4. 7.4.4 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Energy Harvester Selection
      2. 8.1.2 Storage Element Selection
      3. 8.1.3 Inductor Selection
      4. 8.1.4 Capacitor Selection
        1. 8.1.4.1 VREF_SAMP Capacitance
        2. 8.1.4.2 VIN_DC Capacitance
        3. 8.1.4.3 VSTOR Capacitance
        4. 8.1.4.4 Additional Capacitance on VSTOR or VBAT_SEC
    2. 8.2 Typical Applications
      1. 8.2.1 Solar Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 TEG Application Circuit
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
        2. 8.2.3.2 Application Performance Plots
      4. 8.2.4 Piezoelectric Application Circuit
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 Zipファイル
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGT Package
20 Pins
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
5 EN Input Active low digital programming input for enabling/disabling the IC. Connect to GND to enable the IC.
20 LBOOST Input Inductor connection for the boost charger switching node. Connect a 22-µH inductor between this pin and pin 2 (VIN_DC).
6 NC Input Connect to VSS via the IC's PowerPad™.
16 NC Input Connect to ground using the IC's PowerPad.
17 NC Input Connect to ground using the IC's PowerPad.
11 OK_HYST Input Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT_OK hysteresis threshold. If not used, connect this pin to GND.
12 OK_PROG Input Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT_OK threshold. If not used, connect this pin to GND.
13 VBAT_OK Output Digital output for battery good indicator. Internally referenced to the VSTOR voltage. Leave floating if not used.
7 VBAT_OV Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VSTOR = VBAT_SEC overvoltage threshold.
14 VBAT_PRI Input Primary (nonrechargeable) energy storage element HiZ sense input. Leave floating if not used.
18 VBAT_SEC I/O Connect a secondary (rechargeable) storage element with at least 100 µF of equivalent capacitance to this pin.
10 VB_PRI_ON Output Active low push-pull driver for the primary (nonrechargeable) energy storage PMOS FET. Leave floating if not used.
9 VB_SEC_ON Output Active low push-pull driver for the secondary (rechargeable) energy storage PMOS FET. Leave floating if not used.
2 VIN_DC Input DC voltage input from energy harvesters. Connect at least a 4.7-µF capacitor as close as possible between this pin and pin 1.
3 VOC_SAMP Input Sampling pin for MPPT network. Connect to VSTOR to sample at 80% of input soure open circuit voltage. Connect to GND for 50% or connect to the mid-point of external resistor divider between VIN_DC and GND.
4 VREF_SAMP Input Connect a 0.01-µF low-leakage capacitor from this pin to GND to store the voltage to which VIN_DC will be regulated. This voltage is provided by the MPPT sample circuit.
8 VRDIV Output Connect high side of resistor divider networks to this biasing voltage.
1 VSS Input General ground connection for the device
15 VSS Supply Signal ground connection for the device.
19 VSTOR Output Connection for the output of the boost charger, which is typically connected to the system load. Connect at least a 4.7-µF capacitor in parallel with a 0.1-µF capacitor as close as possible to between this pin and pin 1 (VSS).