JAJSGQ0G March   2013  – March 2019

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路図
      2.      充電器の効率と入力電圧との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Power Point Tracking
      2. 7.3.2 Battery Undervoltage Protection
      3. 7.3.3 Battery Overvoltage Protection
      4. 7.3.4 Battery Voltage within Operating Range (VBAT_OK Output)
      5. 7.3.5 Storage Element / Battery Management
      6. 7.3.6 Programming OUT Regulation Voltage
      7. 7.3.7 Step Down (Buck) Converter
      8. 7.3.8 Nano-Power Management and Efficiency
    4. 7.4 Device Functional Modes
      1. 7.4.1 Main Boost Charger Disabled (Ship Mode) - (VSTOR > VSTOR_CHGEN and EN = HIGH)
      2. 7.4.2 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS), EN = don't care)
      3. 7.4.3 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN and EN = LOW )
        1. 7.4.3.1 Buck Converter Enabled (VSTOR > VBAT_UV, EN = LOW and VOUT_EN = HIGH )
      4. 7.4.4 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Energy Harvester Selection
      2. 8.1.2 Storage Element Selection
      3. 8.1.3 Inductor Selection
        1. 8.1.3.1 Boost Charger Inductor Selection
        2. 8.1.3.2 Buck Converter Inductor Selection
      4. 8.1.4 Capacitor Selection
        1. 8.1.4.1 VREF_SAMP Capacitance
        2. 8.1.4.2 VIN_DC Capacitance
        3. 8.1.4.3 VSTOR Capacitance
        4. 8.1.4.4 VOUT Capacitance
        5. 8.1.4.5 Additional Capacitance on VSTOR or VBAT
    2. 8.2 Typical Applications
      1. 8.2.1 Solar Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TEG Application Circuit
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Piezoelectric Application Circuit
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGR Package
20 Pins
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN 5 I Active low digital programming input for enabling/disabling the IC. Connect to GND to enable the IC.
LBOOST 20 I/O Inductor connection for the boost charger switching node. Connect a 22 µH inductor between this pin and pin 2 (VIN_DC).
LBUCK 16 I/O Inductor connection for the buck converter switching node. Connect at least a 4.7 µH inductor between this pin and pin 14 (VOUT).
NC 9 I Connect to ground using the IC's PowerPAD™.
NC 17 I Connect to ground using the IC's PowerPAD.
OK_HYST 10 I Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT_OK hystersis threshold. If not used, connect this pin to GND.
OK_PROG 11 I Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT_OK threshold. If not used, connect this pin to GND.
VBAT 18 I/O Connect a rechargeable storage element with at least 100uF of equivalent capacitance between this pin and either VSS pin.
VBAT_OK 13 O Digital output for battery good indicator. Internally referenced to the VSTOR voltage. Leave floating if not used.
VBAT_OV 7 I Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT overvoltage threshold.
VIN_DC 2 I DC voltage input from energy harvesting source. Connect at least a 4.7 µF capacitor as close as possible between this pin and pin 1.
VOC_SAMP 3 I Sampling pin for MPPT network. Connect to VSTOR to sample at 80% of input source open circuit voltage. Connect to GND for 50% or connect to the mid-point of external resistor divider between VIN_DC and GND.
VOUT 14 O Buck converter output. Connect at least 22 µF output capacitor between this pin and pin 15 (VSS).
VOUT_EN 6 I Active high digital programming input for enabling/disabling the buck converter. Connect to VSTOR to enable the buck converter.
VOUT_SET 12 I Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VOUT regulation set point.
VREF_SAMP 4 I Connect a 0.01-µF low-leakage capacitor from this pin to GND to store the voltage to which VIN_DC will be regulated. This voltage is provided by the MPPT sample circuit.
VRDIV 8 O Connect high side of resistor divider networks to this biasing voltage.
VSS 1 I Power ground for the boost charger.
VSS 15 — Power ground for the buck converter and analog/signal ground for the resistor dividers and VREF_SAMP capacitor.
VSTOR 19 O Connection for the output of the boost charger. Connect at least a 4.7 µF capacitor in parallel with a 0.1 µF capacitor as close as possible to between this pin and pin 1 (VSS).