JAJSDQ0B
June 2017 – March 2022
BQ25600
,
BQ25600D
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Power-On-Reset (POR)
8.3.2
Device Power Up from Battery without Input Source
8.3.3
Power Up from Input Source
8.3.3.1
Power Up REGN Regulation
8.3.3.2
Poor Source Qualification
8.3.3.3
Input Source Type Detection
8.3.3.3.1
D+/D– Detection Sets Input Current Limit in BQ25600D
8.3.3.3.2
PSEL Pins Sets Input Current Limit in BQ25600
8.3.3.4
Input Voltage Limit Threshold Setting (VINDPM Threshold)
8.3.3.5
Converter Power Up
8.3.4
Boost Mode Operation From Battery
8.3.5
Host Mode and Standalone Power Management
8.3.5.1
Host Mode and Default Mode in BQ25600 and BQ25600D
8.3.6
Power Path Management
8.3.7
Battery Charging Management
8.3.7.1
Autonomous Charging Cycle
8.3.7.2
Battery Charging Profile
8.3.7.3
Charging Termination
8.3.7.4
Thermistor Qualification
8.3.7.5
JEITA Guideline Compliance During Charging Mode
8.3.7.6
Boost Mode Thermistor Monitor During Battery Discharge Mode
8.3.7.7
Charging Safety Timer
8.3.8
Protections
8.3.8.1
Voltage and Current Monitoring in Converter Operation
8.3.8.1.1
Voltage and Current Monitoring in Buck Mode
8.3.8.1.1.1
Input Overvoltage (ACOV)
8.3.8.1.1.2
System Overvoltage Protection (SYSOVP)
8.3.8.2
Voltage and Current Monitoring in Boost Mode
8.3.8.2.1
VBUS Soft Start
8.3.8.2.2
VBUS Output Protection
8.3.8.2.3
Boost Mode Overvoltage Protection
8.3.8.3
Thermal Regulation and Thermal Shutdown
8.3.8.3.1
Thermal Protection in Buck Mode
8.3.8.3.2
Thermal Protection in Boost Mode
8.3.8.4
Battery Protection
8.3.8.4.1
Battery Overvoltage Protection (BATOVP)
8.3.8.4.2
Battery Overdischarge Protection
8.3.8.4.3
System Overcurrent Protection
8.4
Device Functional Modes
8.4.1
Narrow VDC Architecture
8.4.2
Dynamic Power Management
8.4.3
Supplement Mode
8.4.4
Shipping Mode and QON Pin
8.4.4.1
BATFET Disable Mode (Shipping Mode)
8.4.4.2
BATFET Enable (Exit Shipping Mode)
8.4.4.3
BATFET Full System Reset
8.4.4.4
QON Pin Operations
8.4.5
Status Outputs ( PG, STAT, INT )
8.4.5.1
Power Good Indicator ( PG Pin and PG_STAT Bit)
8.4.5.2
Charging Status Indicator (STAT)
8.4.5.3
Interrupt to Host ( INT)
8.5
Programming
8.5.1
Serial Interface
8.5.1.1
Data Validity
8.5.1.2
START and STOP Conditions
8.5.1.3
Byte Format
8.5.1.4
Acknowledge (ACK) and Not Acknowledge (NACK)
8.5.1.5
Slave Address and Data Direction Bit
8.5.1.6
Single Read and Write
8.5.1.7
Multi-Read and Multi-Write
8.6
Register Maps
8.6.1
REG00
8.6.2
REG01
8.6.3
REG02
8.6.4
REG03
8.6.5
REG04
8.6.6
REG05
8.6.7
REG06
8.6.8
REG07
8.6.9
REG08
8.6.10
REG09
8.6.11
REG0A
8.6.12
REG0B
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Inductor Selection
9.2.2.2
Input Capacitor
9.2.2.3
Output Capacitor
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
YFF|30
MXBG359A
サーマルパッド・メカニカル・データ
発注情報
jajsdq0b_oa
jajsdq0b_pm
8.5
Programming