JAJSDQ0B June   2017  – March 2022 BQ25600 , BQ25600D

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset (POR)
      2. 8.3.2 Device Power Up from Battery without Input Source
      3. 8.3.3 Power Up from Input Source
        1. 8.3.3.1 Power Up REGN Regulation
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 Input Source Type Detection
          1. 8.3.3.3.1 D+/D– Detection Sets Input Current Limit in BQ25600D
          2. 8.3.3.3.2 PSEL Pins Sets Input Current Limit in BQ25600
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Converter Power Up
      4. 8.3.4 Boost Mode Operation From Battery
      5. 8.3.5 Host Mode and Standalone Power Management
        1. 8.3.5.1 Host Mode and Default Mode in BQ25600 and BQ25600D
      6. 8.3.6 Power Path Management
      7. 8.3.7 Battery Charging Management
        1. 8.3.7.1 Autonomous Charging Cycle
        2. 8.3.7.2 Battery Charging Profile
        3. 8.3.7.3 Charging Termination
        4. 8.3.7.4 Thermistor Qualification
        5. 8.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 8.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode
        7. 8.3.7.7 Charging Safety Timer
      8. 8.3.8 Protections
        1. 8.3.8.1 Voltage and Current Monitoring in Converter Operation
          1. 8.3.8.1.1 Voltage and Current Monitoring in Buck Mode
            1. 8.3.8.1.1.1 Input Overvoltage (ACOV)
            2. 8.3.8.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.3.8.2 Voltage and Current Monitoring in Boost Mode
          1. 8.3.8.2.1 VBUS Soft Start
          2. 8.3.8.2.2 VBUS Output Protection
          3. 8.3.8.2.3 Boost Mode Overvoltage Protection
        3. 8.3.8.3 Thermal Regulation and Thermal Shutdown
          1. 8.3.8.3.1 Thermal Protection in Buck Mode
          2. 8.3.8.3.2 Thermal Protection in Boost Mode
        4. 8.3.8.4 Battery Protection
          1. 8.3.8.4.1 Battery Overvoltage Protection (BATOVP)
          2. 8.3.8.4.2 Battery Overdischarge Protection
          3. 8.3.8.4.3 System Overcurrent Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Narrow VDC Architecture
      2. 8.4.2 Dynamic Power Management
      3. 8.4.3 Supplement Mode
      4. 8.4.4 Shipping Mode and QON Pin
        1. 8.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 8.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 8.4.4.3 BATFET Full System Reset
        4. 8.4.4.4 QON Pin Operations
      5. 8.4.5 Status Outputs ( PG, STAT, INT )
        1. 8.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)
        2. 8.4.5.2 Charging Status Indicator (STAT)
        3. 8.4.5.3 Interrupt to Host ( INT)
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Slave Address and Data Direction Bit
        6. 8.5.1.6 Single Read and Write
        7. 8.5.1.7 Multi-Read and Multi-Write
    6. 8.6 Register Maps
      1. 8.6.1  REG00
      2. 8.6.2  REG01
      3. 8.6.3  REG02
      4. 8.6.4  REG03
      5. 8.6.5  REG04
      6. 8.6.6  REG05
      7. 8.6.7  REG06
      8. 8.6.8  REG07
      9. 8.6.9  REG08
      10. 8.6.10 REG09
      11. 8.6.11 REG0A
      12. 8.6.12 REG0B
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-3A2176FC-EBF6-4FCA-9871-B99375BCE360-low.gifFigure 6-1 BQ25600 YFF Package30-Pin WCSPTop View
GUID-5C6263CD-1A7E-4BBB-8E00-FF5ED8D07165-low.gifFigure 6-2 BQ25600D YFF Package30-Pin WCSPTop View
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME BQ25600 BQ25600D
WCSP WCSP
BAT C1 C1 P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF closely to the BAT pin.
D1 D1
E1 E1
F1 F1
BATSNS F3 F3 AIO Battery voltage sensing pin for charge current regulation. in order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the actual battery pack as close as possible.
BTST C3 C3 P PWM high side driver positive supply. internally, the BTST is connected to the cathode of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE E3 E3 DI Charge enable pin. When this pin is driven low, battery charging is enabled.
D+ — C5 AIO Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2.
D– — D5 AIO Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2.
GND A1 A1 P Ground
B1 B1
INT F4 F4 DO Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report charger device status and fault.
NC B5 B5 No connection. This pin must be floating.
PG D5 — DO Open drain active low power good indicator. Connect to the pull up rail through 10 kΩ resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA.
PMID A3 A3 DO Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Given the total input capacitance, put 1 μF on VBUS to GND, and the rest capacitance on PMID to GND.
B3 B3
PSEL C5 — DI Power source selection input. High indicates 500 mA input current limit. Low indicates 2.4A input current limit. Once the device gets into host mode, the host can program different input current limit to IINDPM register.
QON D4 D4 DI BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE duration turns on BATFET to exit shipping mode. When VBUS is not plugged–in, a logic low of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET to provide full system power reset. The pin contains an internal pull-up to maintain default high logic.
REGN C4 C4 P PWM low side driver positive supply output. internally, REGN is connected to the anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.
SCL F5 F5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA E4 E4 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
STAT E5 E5 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status.
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1Hz
SW A2 A2 P Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
B2 B2
SYS C2 C2 P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 20 µF closely to the SYS pin.
D2 D2
E2 E2
F2 F2
Thermal Pad — — P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.
TS D3 D3 AI Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
VAC A5 A5 AI Input voltage sensing. This pin must be tied to VBUS.
VBUS A4 A4 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as possible to IC.
B4 B4
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power