JAJSDQ0B June   2017  – March 2022 BQ25600 , BQ25600D

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset (POR)
      2. 8.3.2 Device Power Up from Battery without Input Source
      3. 8.3.3 Power Up from Input Source
        1. 8.3.3.1 Power Up REGN Regulation
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 Input Source Type Detection
          1. 8.3.3.3.1 D+/D– Detection Sets Input Current Limit in BQ25600D
          2. 8.3.3.3.2 PSEL Pins Sets Input Current Limit in BQ25600
        4. 8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.3.3.5 Converter Power Up
      4. 8.3.4 Boost Mode Operation From Battery
      5. 8.3.5 Host Mode and Standalone Power Management
        1. 8.3.5.1 Host Mode and Default Mode in BQ25600 and BQ25600D
      6. 8.3.6 Power Path Management
      7. 8.3.7 Battery Charging Management
        1. 8.3.7.1 Autonomous Charging Cycle
        2. 8.3.7.2 Battery Charging Profile
        3. 8.3.7.3 Charging Termination
        4. 8.3.7.4 Thermistor Qualification
        5. 8.3.7.5 JEITA Guideline Compliance During Charging Mode
        6. 8.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode
        7. 8.3.7.7 Charging Safety Timer
      8. 8.3.8 Protections
        1. 8.3.8.1 Voltage and Current Monitoring in Converter Operation
          1. 8.3.8.1.1 Voltage and Current Monitoring in Buck Mode
            1. 8.3.8.1.1.1 Input Overvoltage (ACOV)
            2. 8.3.8.1.1.2 System Overvoltage Protection (SYSOVP)
        2. 8.3.8.2 Voltage and Current Monitoring in Boost Mode
          1. 8.3.8.2.1 VBUS Soft Start
          2. 8.3.8.2.2 VBUS Output Protection
          3. 8.3.8.2.3 Boost Mode Overvoltage Protection
        3. 8.3.8.3 Thermal Regulation and Thermal Shutdown
          1. 8.3.8.3.1 Thermal Protection in Buck Mode
          2. 8.3.8.3.2 Thermal Protection in Boost Mode
        4. 8.3.8.4 Battery Protection
          1. 8.3.8.4.1 Battery Overvoltage Protection (BATOVP)
          2. 8.3.8.4.2 Battery Overdischarge Protection
          3. 8.3.8.4.3 System Overcurrent Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Narrow VDC Architecture
      2. 8.4.2 Dynamic Power Management
      3. 8.4.3 Supplement Mode
      4. 8.4.4 Shipping Mode and QON Pin
        1. 8.4.4.1 BATFET Disable Mode (Shipping Mode)
        2. 8.4.4.2 BATFET Enable (Exit Shipping Mode)
        3. 8.4.4.3 BATFET Full System Reset
        4. 8.4.4.4 QON Pin Operations
      5. 8.4.5 Status Outputs ( PG, STAT, INT )
        1. 8.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)
        2. 8.4.5.2 Charging Status Indicator (STAT)
        3. 8.4.5.3 Interrupt to Host ( INT)
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Slave Address and Data Direction Bit
        6. 8.5.1.6 Single Read and Write
        7. 8.5.1.7 Multi-Read and Multi-Write
    6. 8.6 Register Maps
      1. 8.6.1  REG00
      2. 8.6.2  REG01
      3. 8.6.3  REG02
      4. 8.6.4  REG03
      5. 8.6.5  REG04
      6. 8.6.6  REG05
      7. 8.6.7  REG06
      8. 8.6.8  REG07
      9. 8.6.9  REG08
      10. 8.6.10 REG09
      11. 8.6.11 REG0A
      12. 8.6.12 REG0B
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.7.7 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is two hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher than VBATLOWV threshold.

The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be disabled through I2C by setting EN_TIMER bit.

During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to five hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

During the fault, timer is suspended. Once the fault goes away, the timer resumes counting. If user stops the current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).