SLUSFA3 Data sheet

JAJSQM6B June 2023 – February 2024 BQ25622E

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RYK|18
- MPQF634

サーマルパッド・メカニカル・データ

発注情報

8.6.2 BQ25622E Registers

Table 8-5 lists the memory-mapped registers for the BQ25622E registers. All register offset addresses not listed in Table 8-5 should be considered as reserved locations and the register contents should not be modified.

Table 8-5 BQ25622E Registers

Address	Acronym	Register Name	Section
2h	REG0x02_Charge_Current_Limit	Charge Current Limit	Go
4h	REG0x04_Charge_Voltage_Limit	Charge Voltage Limit	Go
6h	REG0x06_Input_Current_Limit	Input Current Limit	Go
8h	REG0x08_Input_Voltage_Limit	Input Voltage Limit	Go
Eh	REG0x0E_Minimal_System_Voltage	Minimal System Voltage	Go
10h	REG0x10_Pre-charge_Control	Pre-charge Control	Go
12h	REG0x12_Termination_Control	Termination Control	Go
14h	REG0x14_Charge_Control_0	Charge Control 0	Go
15h	REG0x15_Charge_Timer_Control	Charge Timer Control	Go
16h	REG0x16_Charger_Control_1	Charger Control 1	Go
17h	REG0x17_Charger_Control_2	Charger Control 2	Go
18h	REG0x18_Charger_Control_3	Charger Control 3	Go
19h	REG0x19_Charger_Control_4	Charger Control 4	Go
1Ah	REG0x1A_NTC_Control_0	NTC Control 0	Go
1Bh	REG0x1B_NTC_Control_1	NTC Control 1	Go
1Ch	REG0x1C_NTC_Control_2	NTC Control 2	Go
1Dh	REG0x1D_Charger_Status_0	Charger Status 0	Go
1Eh	REG0x1E_Charger_Status_1	Charger Status 1	Go
1Fh	REG0x1F_FAULT_Status_0	FAULT Status 0	Go
20h	REG0x20_Charger_Flag_0	Charger Flag 0	Go
21h	REG0x21_Charger_Flag_1	Charger Flag 1	Go
22h	REG0x22_FAULT_Flag_0	FAULT Flag 0	Go
23h	REG0x23_Charger_Mask_0	Charger Mask 0	Go
24h	REG0x24_Charger_Mask_1	Charger Mask 1	Go
25h	REG0x25_FAULT_Mask_0	FAULT Mask 0	Go
26h	REG0x26_ADC_Control	ADC Control	Go
27h	REG0x27_ADC_Function_Disable_0	ADC Function Disable 0	Go
28h	REG0x28_IBUS_ADC	IBUS ADC	Go
2Ah	REG0x2A_IBAT_ADC	IBAT ADC	Go
2Ch	REG0x2C_VBUS_ADC	VBUS ADC	Go
2Eh	REG0x2E_VPMID_ADC	VPMID ADC	Go
30h	REG0x30_VBAT_ADC	VBAT ADC	Go
32h	REG0x32_VSYS_ADC	VSYS ADC	Go
34h	REG0x34_TS_ADC	TS ADC	Go
36h	REG0x36_TDIE_ADC	TDIE ADC	Go
38h	REG0x38_Part_Information	Part Information	Go

Complex bit access types are encoded to fit into small table cells. Table 8-6 shows the codes that are used for access types in this section.

Table 8-6 BQ25622E Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.6.2.1 REG0x02_Charge_Current_Limit Register (Address = 2h) [Reset = 0340h]

REG0x02_Charge_Current_Limit is shown in Figure 8-15 and described in Table 8-7.

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Charge Current Limit

Figure 8-15 REG0x02_Charge_Current_Limit Register

15	14	13	12	11	10	9	8
RESERVED				ICHG
R-0h				R/W-Dh

7	6	5	4	3	2	1	0
ICHG		RESERVED
R/W-Dh		R-0h

Table 8-7 REG0x02_Charge_Current_Limit Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0h	Reserved
11:6	ICHG	R/W	Dh	Charge Current Regulation Limit: This 16-bit register follows the little-endian convention. ICHG[5:2] falls in REG0x03[3:0], and ICHG[1:0] falls in REG0x02[7:6]. POR: 1040mA (Dh) Range: 80mA-3040mA (1h-26h) Clamped Low Clamped High Bit Step: 80mA (1h) NOTE: When Q4_FULLON=1, this register has a minimum value of 160mA
5:0	RESERVED	R	0h	Reserved

8.6.2.2 REG0x04_Charge_Voltage_Limit Register (Address = 4h) [Reset = 0D20h]

REG0x04_Charge_Voltage_Limit is shown in Figure 8-16 and described in Table 8-8.

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Charge Voltage Limit

Figure 8-16 REG0x04_Charge_Voltage_Limit Register

15	14	13	12	11	10	9	8
RESERVED				VREG
R-0h				R/W-1A4h

7	6	5	4	3	2	1	0
VREG					RESERVED
R/W-1A4h					R-0h

Table 8-8 REG0x04_Charge_Voltage_Limit Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0h	Reserved
11:3	VREG	R/W	1A4h	Battery Voltage Regulation Limit: This 16-bit register follows the little-endian convention. VREG[8:5] falls in REG0x05[3:0], and VREG[4:0] falls in REG0x04[7:3]. POR: 4200mV (1A4h) Range: 3500mV-4800mV (15Eh-1E0h) Clamped Low Clamped High Bit Step: 10mV
2:0	RESERVED	R	0h	Reserved

8.6.2.3 REG0x06_Input_Current_Limit Register (Address = 6h) [Reset = 0A00h]

REG0x06_Input_Current_Limit is shown in Figure 8-17 and described in Table 8-9.

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Input Current Limit

Figure 8-17 REG0x06_Input_Current_Limit Register

15	14	13	12	11	10	9	8
RESERVED				IINDPM
R-0h				R/W-A0h

7	6	5	4	3	2	1	0
IINDPM				RESERVED
R/W-A0h				R-0h

Table 8-9 REG0x06_Input_Current_Limit Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0h	Reserved
11:4	IINDPM	R/W	A0h	Input Current Regulation Limit: This 16-bit register follows the little-endian convention. POR: 3200mA (A0h) Range: 100mA-3200mA (5h-A0h) Clamped Low Clamped High Bit Step: 20mA When the adapter is removed, IINDPM is reset to its POR value of 3.2 A.
3:0	RESERVED	R	0h	Reserved

8.6.2.4 REG0x08_Input_Voltage_Limit Register (Address = 8h) [Reset = 0E60h]

REG0x08_Input_Voltage_Limit is shown in Figure 8-18 and described in Table 8-10.

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Input Voltage Limit

Figure 8-18 REG0x08_Input_Voltage_Limit Register

15	14	13	12	11	10	9	8
RESERVED		VINDPM
R-0h		R/W-73h

7	6	5	4	3	2	1	0
VINDPM			RESERVED
R/W-73h			R-0h

Table 8-10 REG0x08_Input_Voltage_Limit Register Field Descriptions

Bit	Field	Type	Reset	Description
15:14	RESERVED	R	0h	Reserved
13:5	VINDPM	R/W	73h	Absolute Input Voltage Regulation Limit: This 16-bit register follows the little-endian convention. VINDPM[8:3] falls in REG0x09[5:0], and VINDPM[2:0] falls in REG0x08[7:5]. POR: 4600mV (73h) Range: 3800mV-16800mV (5Fh-1A4h) Clamped Low Clamped High Bit Step: 40mV
4:0	RESERVED	R	0h	Reserved

8.6.2.5 REG0x0E_Minimal_System_Voltage Register (Address = Eh) [Reset = 0B00h]

REG0x0E_Minimal_System_Voltage is shown in Figure 8-19 and described in Table 8-11.

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Minimal System Voltage

Figure 8-19 REG0x0E_Minimal_System_Voltage Register

15	14	13	12	11	10	9	8
RESERVED				VSYSMIN
R-0h				R/W-2Ch

7	6	5	4	3	2	1	0
VSYSMIN		RESERVED
R/W-2Ch		R-0h

Table 8-11 REG0x0E_Minimal_System_Voltage Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0h	Reserved
11:6	VSYSMIN	R/W	2Ch	Minimal System Voltage: This 16-bit register follows the little-endian convention. VSYSMIN[5:2] falls in REG0x0F[3:0], and VSYSMIN[1:0] falls in REG0x0E[7:6]. POR: 3520mV (2Ch) Range: 2560mV-3840mV (20h-30h) Clamped Low Clamped High Bit Step: 80mV
5:0	RESERVED	R	0h	Reserved

8.6.2.6 REG0x10_Pre-charge_Control Register (Address = 10h) [Reset = 0050h]

REG0x10_Pre-charge_Control is shown in Figure 8-20 and described in Table 8-12.

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Pre-charge Control

Figure 8-20 REG0x10_Pre-charge_Control Register

15	14	13	12	11	10	9	8
RESERVED							IPRECHG
R-0h							R/W-5h

7	6	5	4	3	2	1	0
IPRECHG				RESERVED
R/W-5h				R-0h

Table 8-12 REG0x10_Pre-charge_Control Register Field Descriptions

Bit	Field	Type	Reset	Description
15:9	RESERVED	R	0h	Reserved
8:4	IPRECHG	R/W	5h	Pre-charge current regulation limit: This 16-bit register follows the little-endian convention. IPRECHG[4] falls in REG0x11[0], and IPRECHG[3:0] falls in REG0x10[7:4] POR: 100mA (5h) Range: 20mA-620mA (1h-1Fh) Clamped Low Bit Step: 20mA (1h) NOTE: When Q4_FULLON=1, this register has a minimum value of 80mA
3:0	RESERVED	R	0h	Reserved

8.6.2.7 REG0x12_Termination_Control Register (Address = 12h) [Reset = 0030h]

REG0x12_Termination_Control is shown in Figure 8-21 and described in Table 8-13.

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Termination Control

Figure 8-21 REG0x12_Termination_Control Register

15	14	13	12	11	10	9	8
RESERVED							ITERM
R-0h							R/W-6h

7	6	5	4	3	2	1	0
ITERM					RESERVED
R/W-6h					R-0h

Table 8-13 REG0x12_Termination_Control Register Field Descriptions

Bit	Field	Type	Reset	Description
15:9	RESERVED	R	0h	Reserved
8:3	ITERM	R/W	6h	Termination Current Threshold: This 16-bit register follows the little-endian convention. ITERM[5] falls in REG0x13[0], and ITERM[4:0] falls in REG0x12[7:3]. POR: 60mA (6h) Range: 10mA-620mA (1h-3Eh) Clamped Low Bit Step: 10mA (1h) NOTE: When Q4_FULLON=1, this register has a minimum value of 120mA, so Reset value becomes 120mA in this case
2:0	RESERVED	R	0h	Reserved

8.6.2.8 REG0x14_Charge_Control_0 Register (Address = 14h) [Reset = 06h]

REG0x14_Charge_Control_0 is shown in Figure 8-22 and described in Table 8-14.

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Charge Control 0

Figure 8-22 REG0x14_Charge_Control_0 Register

7	6	5	4	3	2	1	0
Q1_FULLON	Q4_FULLON	ITRICKLE	TOPOFF_TMR		EN_TERM	VINDPM_BAT_TRACK	VRECHG
R/W-0h	R/W-0h	R/W-0h	R/W-0h		R/W-1h	R/W-1h	R/W-0h

Table 8-14 REG0x14_Charge_Control_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	Q1_FULLON	R/W	0h	Forces RBFET (Q1) into low resistance state (26 mΩ) , regardless of IINDPM setting. 0h = RBFET RDSON determined by IINDPM setting (default) 1h = RBFET RDSON is always 26 mΩ
6	Q4_FULLON	R/W	0h	Forces BATFET (Q4) into low resistance state (15 mΩ), regardless of ICHG setting. (Only applies when VBAT > VSYSMIN. Otherwise BATFET operates in linear mode.) 0h = BATFET RDSON determined by charge current (default) 1h = BATFET RDSON is always 15 mΩ
5	ITRICKLE	R/W	0h	Trickle charging current setting: 0b = 20mA (default) 1b = 80mA
4:3	TOPOFF_TMR	R/W	0h	Top-off timer control: 0h = Disabled (default) 1h = 17 mins 2h = 35 mins 3h = 52 mins
2	EN_TERM	R/W	1h	Enable termination 0h = Disable 1h = Enable (default)
1	VINDPM_BAT_TRACK	R/W	1h	Sets VINDPM to track BAT voltage. Actual VINDPM is higher of the VINDPM register value and VBAT + VINDPM_BAT_TRACK. 0h = Disable function (VINDPM set by register) 1h = VBAT + 400 mV (default)
0	VRECHG	R/W	0h	Battery Recharge Threshold Offset (Below VREG) 0h = 100mV (default) 1h = 200mV

8.6.2.9 REG0x15_Charge_Timer_Control Register (Address = 15h) [Reset = 0Ch]

REG0x15_Charge_Timer_Control is shown in Figure 8-23 and described in Table 8-15.

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Charge Timer Control

Figure 8-23 REG0x15_Charge_Timer_Control Register

7	6	5	4	3	2	1	0
DIS_STAT	RESERVED			TMR2X_EN	EN_SAFETY_TMRS	PRECHG_TMR	CHG_TMR
R/W-0h	R-0h			R/W-1h	R/W-1h	R/W-0h	R/W-0h

Table 8-15 REG0x15_Charge_Timer_Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DIS_STAT	R/W	0h	Disable the STAT pin output 0h = Enable (default) 1h = Disable
6:4	RESERVED	R	0h	Reserved
3	TMR2X_EN	R/W	1h	2X charging timer control 0h = Trickle charge, pre-charge and fast charge timer not slowed by 2X during input DPM or thermal regulation. 1h = Trickle charge, pre-charge and fast charge timer slowed by 2X during input DPM or thermal regulation (default)
2	EN_SAFETY_TMRS	R/W	1h	Enable fast charge, pre-charge and trickle charge timers 0h = Disable 1h = Enable (default)
1	PRECHG_TMR	R/W	0h	Pre-charge safety timer setting 0h = 2.5 hrs (default) 1h = 0.62 hrs
0	CHG_TMR	R/W	0h	Fast charge safety timer setting 0h = 14.5 hrs (default) 1h = 28 hrs

8.6.2.10 REG0x16_Charger_Control_1 Register (Address = 16h) [Reset = A1h]

REG0x16_Charger_Control_1 is shown in Figure 8-24 and described in Table 8-16.

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Charger Control 1

Figure 8-24 REG0x16_Charger_Control_1 Register

7	6	5	4	3	2	1	0
EN_AUTO_IBATDIS	FORCE_IBATDIS	EN_CHG	EN_HIZ	FORCE_PMID_DIS	WD_RST	WATCHDOG
R/W-1h	R/W-0h	R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-1h

Table 8-16 REG0x16_Charger_Control_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EN_AUTO_IBATDIS	R/W	1h	Enable the auto battery discharging during the battery OVP fault 0h = The charger does NOT apply a discharging current on BAT during battery OVP triggered 1h = The charger does apply a discharging current on BAT during battery OVP triggered (default)
6	FORCE_IBATDIS	R/W	0h	Force a battery discharging current (~30mA) 0h = IDLE (default) 1h = Force the charger to apply a discharging current on BAT
5	EN_CHG	R/W	1h	Charger enable configuration 0h = Charge Disable 1h = Charge Enable (default)
4	EN_HIZ	R/W	0h	Enable HIZ mode. 0h = Disable (default) 1h = Enable
3	FORCE_PMID_DIS	R/W	0h	Force a PMID discharge current (~30mA.) 0h = Disable (default) 1h = Enable
2	WD_RST	R/W	0h	I2C watch dog timer reset 0h = Normal (default) 1h = Reset (this bit goes back to 0 after timer reset)
1:0	WATCHDOG	R/W	1h	Watchdog timer setting 0h = Disable 1h = 50s (default) 2h = 100s 3h = 200s

8.6.2.11 REG0x17_Charger_Control_2 Register (Address = 17h) [Reset = 4Fh]

REG0x17_Charger_Control_2 is shown in Figure 8-25 and described in Table 8-17.

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Charger Control 2

Figure 8-25 REG0x17_Charger_Control_2 Register

7	6	5	4	3	2	1	0
REG_RST	TREG	SET_CONV_FREQ		SET_CONV_STRN		RESERVED	VBUS_OVP
R/W-0h	R/W-1h	R/W-0h		R/W-3h		R-0h	R/W-1h

Table 8-17 REG0x17_Charger_Control_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	REG_RST	R/W	0h	Reset registers to default values and reset timer Value resets to 0 after reset completes. 0h = Not reset (default) 1h = Reset
6	TREG	R/W	1h	Thermal regulation thresholds. 0h = 60C 1h = 120C (default)
5:4	SET_CONV_FREQ	R/W	0h	Adjust switching frequency of the converter 0h = Nominal, 1.5 MHz (default) 1h = -10%, 1.35 MHz 2h = +10%, 1.65 MHz 3h = RESERVED
3:2	SET_CONV_STRN	R/W	3h	Adjust the high side and low side drive strength of the converter to adjust efficiency versus EMI. 0h = weak 1h = normal 2h = RESERVED 3h = strong
1	RESERVED	R	0h	Reserved
0	VBUS_OVP	R/W	1h	Sets VBUS overvoltage protection threshold 0h = 6.3 V 1h = 18.5 V

8.6.2.12 REG0x18_Charger_Control_3 Register (Address = 18h) [Reset = 04h]

REG0x18_Charger_Control_3 is shown in Figure 8-26 and described in Table 8-18.

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Charger Control 3

Figure 8-26 REG0x18_Charger_Control_3 Register

7	6	5	4	3	2	1	0
RESERVED			PFM_FWD_DIS	BATFET_CTRL_WVBUS	BATFET_DLY	BATFET_CTRL
R-0h			R/W-0h	R/W-0h	R/W-1h	R/W-0h

Table 8-18 REG0x18_Charger_Control_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	PFM_FWD_DIS	R/W	0h	Disable PFM in forward buck mode 0h = Enable (Default) 1h = Disable
3	BATFET_CTRL_WVBUS	R/W	0h	Optionally allows BATFET off or system power reset with adapter present. 0h = 0x0 1h = 0x1
2	BATFET_DLY	R/W	1h	Delay time added to the taking action in bits [1:0] of the BATFET_CTRL 0h = Add 20 ms delay time 1h = Add 10s delay time (default)
1:0	BATFET_CTRL	R/W	0h	BATFET control The control logic of the BATFET to force the device enter different modes. 0h = Normal (default) 1h = Shutdown Mode 2h = Ship Mode 3h = System Power Reset

8.6.2.13 REG0x19_Charger_Control_4 Register (Address = 19h) [Reset = C0h]

REG0x19_Charger_Control_4 is shown in Figure 8-27 and described in Table 8-19.

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Charger Control 4

Figure 8-27 REG0x19_Charger_Control_4 Register

7	6	5	4	3	2	1	0
IBAT_PK		VBAT_UVLO	RESERVED		EN_EXTILIM	CHG_RATE
R/W-3h		R/W-0h	R-0h		R/W-0h	R/W-0h

Table 8-19 REG0x19_Charger_Control_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	IBAT_PK	R/W	3h	Battery discharging peak current protection threshold setting 0h = 1.5A 1h = 3A 2h = 6A 3h = 12A (default)
5	VBAT_UVLO	R/W	0h	Select the VBAT_UVLO falling threshold and VBAT_SHORT threshold 0h = VBAT_UVLO 2.2V, VBAT_SHORT 2.05V (default) 1h = VBAT_UVLO 1.8V, VBAT_SHORT 1.85V
4:3	RESERVED	R	0h	Reserved
2	EN_EXTILIM	R/W	0h	Enable the external ILIM pin input current regulation 0b = Disabled 1b = Enabled (default)
1:0	CHG_RATE	R/W	0h	The charge rate definition for the fast charge stage. The charging current fold back value is equal to ICHG register setting times the fold back ratio, then divided by the charge rate. 0h = 1C (default) 1h = 2C 2h = 4C 3h = 6C

8.6.2.14 REG0x1A_NTC_Control_0 Register (Address = 1Ah) [Reset = 0Dh]

REG0x1A_NTC_Control_0 is shown in Figure 8-28 and described in Table 8-20.

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NTC Control 0

Figure 8-28 REG0x1A_NTC_Control_0 Register

7	6	5	4	3	2	1	0
TS_IGNORE	RESERVED			TS_ISET_WARM		TS_ISET_COOL
R/W-0h	R-0h			R/W-3h		R/W-1h

Table 8-20 REG0x1A_NTC_Control_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TS_IGNORE	R/W	0h	Ignore the TS feedback: the charger considers the TS is always good to allow charging, TS_STAT reports TS_NORMAL condition. 0h = Not ignore (Default) 1h = Ignore
6:4	RESERVED	R	0h	Reserved
3:2	TS_ISET_WARM	R/W	3h	TS_WARM Current Setting 0h = Charge Suspend 1h = Set ICHG to 20% 2h = Set ICHG to 40% 3h = ICHG unchanged (default)
1:0	TS_ISET_COOL	R/W	1h	TS_COOL Current Setting 0h = Charge Suspend 1h = Set ICHG to 20% (default) 2h = Set ICHG to 40% 3h = ICHG unchanged

8.6.2.15 REG0x1B_NTC_Control_1 Register (Address = 1Bh) [Reset = 25h]

REG0x1B_NTC_Control_1 is shown in Figure 8-29 and described in Table 8-21.

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NTC Control 1

Figure 8-29 REG0x1B_NTC_Control_1 Register

7	6	5	4	3	2	1	0
TS_TH1_TH2_TH3			TS_TH4_TH5_TH6			TS_VSET_WARM
R/W-1h			R/W-1h			R/W-1h

Table 8-21 REG0x1B_NTC_Control_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	TS_TH1_TH2_TH3	R/W	1h	TH1, TH2 and TH3 comparator falling temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ. 0h = TH1 is 0°C, TH2 is 5°C, TH3 is 15°C 1h = TH1 is 0°C, TH2 is 10°C, TH3 is 15°C (default) 2h = TH1 is 0°C, TH2 is 15°C, TH3 is 20°C 3h = TH1 is 0°C, TH2 is 20°C, TH3 20°C 4h = TH1 is -5°C, TH2 is 5°C, TH3 is 15°C 5h = TH1 is -5°C, TH2 is 10°C, TH3 is 15°C 6h = TH1 is -5°C, TH2 is 10°C, TH3 is 20°C 7h = TH1 is 0°C, TH2 is 10°C, TH3 is 20°C
4:2	TS_TH4_TH5_TH6	R/W	1h	TH4, TH5 and TH6 comparator rising temperature thresholds when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ. 0h = TH4 is 35°C, TH5 is 40°C, TH6 is 60°C 1h = TH4 is 35°C, TH5 is 45°C, TH6 is 60°C (default) 2h = TH4 is 35°C, TH5 is 50°C, TH6 is 60°C 3h = TH4 is 40°C, TH5 is 55°C, TH6 is 60°C 4h = TH4 is 35°C, TH5 is 40°C, TH6 is 50°C 5h = TH4 is 35°C, TH5 is 45°C, TH6 is 50°C 6h = TH4 is 40°C, TH5 is 45°C, TH6 is 60°C 7h = TH4 is 40°C, TH5 is 50°C, TH6 is 60°C
1:0	TS_VSET_WARM	R/W	1h	TS_WARM Voltage Setting 0h = Set VREG to VREG-300mV 1h = Set VREG to VREG-200mV (default) 2h = Set VREG to VREG-100mV 3h = VREG unchanged

8.6.2.16 REG0x1C_NTC_Control_2 Register (Address = 1Ch) [Reset = 3Fh]

REG0x1C_NTC_Control_2 is shown in Figure 8-30 and described in Table 8-22.

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NTC Control 2

Figure 8-30 REG0x1C_NTC_Control_2 Register

7	6	5	4	3	2	1	0
RESERVED	TS_VSET_SYM	TS_VSET_PREWARM		TS_ISET_PREWARM		TS_ISET_PRECOOL
R-0h	R/W-0h	R/W-3h		R/W-3h		R/W-3h

Table 8-22 REG0x1C_NTC_Control_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	TS_VSET_SYM	R/W	0h	When this bit is set to 0, the voltage regulation for TS_PRECOOL and TS_COOL is unchanged. When this bit is set to 1, TS_PRECOOL uses the TS_VSET_PREWARM setting of TS_PREWARM and TS_COOL uses the TS_VSET_WARM setting of TS_WARM . 0h = VREG unchanged (default) 1h = TS_COOLx matches TS_WARMx
5:4	TS_VSET_PREWARM	R/W	3h	Advanced temperature profile voltage setting for TS_PREWARM (TH4 - TH5) 0h = Set VREG to VREG-300mV 1h = Set VREG to VREG-200mV 2h = Set VREG to VREG-100mV 3h = VREG unchanged (default)
3:2	TS_ISET_PREWARM	R/W	3h	Advanced temperature profile current setting for TS_PREWARM zone(TH4 - TH5) 0h = Charge Suspend 1h = Set ICHG to 20% 2h = Set ICHG to 40% 3h = ICHG unchanged (default)
1:0	TS_ISET_PRECOOL	R/W	3h	Advanced temperature profile current setting for TS_PRECOOL zone (TH2 - TH3) 0h = Charge Suspend 1h = Set ICHG to 20% 2h = Set ICHG to 40% 3h = ICHG unchanged (default)

8.6.2.17 REG0x1D_Charger_Status_0 Register (Address = 1Dh) [Reset = 00h]

REG0x1D_Charger_Status_0 is shown in Figure 8-31 and described in Table 8-23.

Return to the Summary Table.

Charger Status 0

Figure 8-31 REG0x1D_Charger_Status_0 Register

7	6	5	4	3	2	1	0
RESERVED	ADC_DONE_STAT	TREG_STAT	VSYS_STAT	IINDPM_STAT	VINDPM_STAT	SAFETY_TMR_STAT	WD_STAT
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-23 REG0x1D_Charger_Status_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	ADC_DONE_STAT	R	0h	ADC Conversion Status (in one-shot mode only) Note: Always reads 0 in continuous mode 0h = Conversion not complete 1h = Conversion complete
5	TREG_STAT	R	0h	IC Thermal regulation status 0h = Normal 1h = Device in thermal regulation
4	VSYS_STAT	R	0h	VSYS Regulation Status (forward mode) 0h = Not in VSYSMIN regulation (BAT>VSYSMIN) 1h = In VSYSMIN regulation (BAT<VSYSMIN)
3	IINDPM_STAT	R	0h	In forward mode, indicates that either IINDPM regulation is active or ILIM pin regulation is active 0h = Normal 1h = In IINDPM/ILIM regulation
2	VINDPM_STAT	R	0h	VINDPM status (forward mode) 0h = Normal 1h = In VINDPM regulation
1	SAFETY_TMR_STAT	R	0h	Fast charge, trickle charge and pre-charge timer status 0h = Normal 1h = Safety timer expired
0	WD_STAT	R	0h	I2C watch dog timer status 0h = Normal 1h = WD timer expired

8.6.2.18 REG0x1E_Charger_Status_1 Register (Address = 1Eh) [Reset = 00h]

REG0x1E_Charger_Status_1 is shown in Figure 8-32 and described in Table 8-24.

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Charger Status 1

Figure 8-32 REG0x1E_Charger_Status_1 Register

7	6	5	4	3	2	1	0
RESERVED			CHG_STAT		VBUS_STAT
R-0h			R-0h		R-0h

Table 8-24 REG0x1E_Charger_Status_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4:3	CHG_STAT	R	0h	Charge Status bits 0h = Not Charging or Charge Terminated 1h = Trickle Charge, Pre-charge or Fast charge (CC mode) 2h = Taper Charge (CV mode) 3h = Top-off Timer Active Charging
2:0	VBUS_STAT	R	0h	VBUS status bits 100b = Unknown Adapter (default IINDPM setting)

8.6.2.19 REG0x1F_FAULT_Status_0 Register (Address = 1Fh) [Reset = 00h]

REG0x1F_FAULT_Status_0 is shown in Figure 8-33 and described in Table 8-25.

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FAULT Status 0

Figure 8-33 REG0x1F_FAULT_Status_0 Register

7	6	5	4	3	2	1	0
VBUS_FAULT_STAT	BAT_FAULT_STAT	SYS_FAULT_STAT	RESERVED	TSHUT_STAT	TS_STAT
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-25 REG0x1F_FAULT_Status_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VBUS_FAULT_STAT	R	0h	VBUS fault status, VBUS OVP and sleep comparator 0h = Normal 1h = Device not switching due to over voltage protection or sleep comparator
6	BAT_FAULT_STAT	R	0h	BAT fault status, IBAT OCP and VBAT OVP 0h = Normal 1h = Device in battery over current protection or battery overvoltage protection
5	SYS_FAULT_STAT	R	0h	VSYS under voltage and over voltage status 0h = Normal 1h = SYS in SYS short circuit or over voltage
4	RESERVED	R	0h	Reserved
3	TSHUT_STAT	R	0h	IC temperature shutdown status 0h = Normal 1h = Device in thermal shutdown protection
2:0	TS_STAT	R	0h	The TS temperature zone. 0h = TS_NORMAL 1h = TS_COLDor TS resistor string power rail is not available. 2h = TS_HOT 3h = TS_COOL 4h = TS_WARM 5h = TS_PRECOOL 6h = TS_PREWARM 7h = TS pin bias reference fault

8.6.2.20 REG0x20_Charger_Flag_0 Register (Address = 20h) [Reset = 00h]

REG0x20_Charger_Flag_0 is shown in Figure 8-34 and described in Table 8-26.

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Charger Flag 0

Figure 8-34 REG0x20_Charger_Flag_0 Register

7	6	5	4	3	2	1	0
RESERVED	ADC_DONE_FLAG	TREG_FLAG	VSYS_FLAG	IINDPM_FLAG	VINDPM_FLAG	SAFETY_TMR_FLAG	WD_FLAG
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-26 REG0x20_Charger_Flag_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	ADC_DONE_FLAG	R	0h	ADC conversion flag (only in one-shot mode) 0h = Conversion not completed 1h = Conversion completed
5	TREG_FLAG	R	0h	IC Thermal regulation flag 0h = Normal 1h = TREG signal rising threshold detected
4	VSYS_FLAG	R	0h	VSYS min regulation flag 0h = Normal 1h = Entered or existed VSYS min regulation
3	IINDPM_FLAG	R	0h	Indicates that either the IINDPM regulation loop or ILIM pin regulatio has been entered. 0h = Normal 1h = IINDPM or ILIM regulation signal rising edge detected
2	VINDPM_FLAG	R	0h	VINDPM flag 0h = Normal 1h = VINDPM regulation signal rising edge detected
1	SAFETY_TMR_FLAG	R	0h	Fast charge, trickle charge and pre-charge timer flag 0h = Normal 1h = Fast charge timer expired rising edge detected
0	WD_FLAG	R	0h	I2C watchdog timer flag 0h = Normal 1h = WD timer signal rising edge detected

8.6.2.21 REG0x21_Charger_Flag_1 Register (Address = 21h) [Reset = 00h]

REG0x21_Charger_Flag_1 is shown in Figure 8-35 and described in Table 8-27.

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Charger Flag 1

Figure 8-35 REG0x21_Charger_Flag_1 Register

7	6	5	4	3	2	1	0
RESERVED				CHG_FLAG	RESERVED		VBUS_FLAG
R-0h				R-0h	R-0h		R-0h

Table 8-27 REG0x21_Charger_Flag_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	CHG_FLAG	R	0h	Charge status flag 0h = Normal 1h = Charge status changed
2:1	RESERVED	R	0h	Reserved
0	VBUS_FLAG	R	0h	VBUS status flag 0h = Normal 1h = VBUS status changed

8.6.2.22 REG0x22_FAULT_Flag_0 Register (Address = 22h) [Reset = 00h]

REG0x22_FAULT_Flag_0 is shown in Figure 8-36 and described in Table 8-28.

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FAULT Flag 0

Figure 8-36 REG0x22_FAULT_Flag_0 Register

7	6	5	4	3	2	1	0
VBUS_FAULT_FLAG	BAT_FAULT_FLAG	SYS_FAULT_FLAG	RESERVED	TSHUT_FLAG	RESERVED		TS_FLAG
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h		R-0h

Table 8-28 REG0x22_FAULT_Flag_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VBUS_FAULT_FLAG	R	0h	VBUS over-voltage or sleep flag 0h = Normal 1h = Entered VBUS OVP or sleep
6	BAT_FAULT_FLAG	R	0h	IBAT over-current and VBAT over-voltage flag 0h = Normal 1h = Entered battery discharged OCP or VBAT OVP
5	SYS_FAULT_FLAG	R	0h	VSYS over voltage and SYS short flag 0h = Normal 1h = Stopped switching due to system over-voltage or SYS short fault
4	RESERVED	R	0h	Reserved
3	TSHUT_FLAG	R	0h	IC thermal shutdown flag 0h = Normal 1h = TS shutdown signal rising threshold detected
2:1	RESERVED	R	0h	Reserved
0	TS_FLAG	R	0h	TS status flag 0h = Normal 1h = A change to TS status was detected

8.6.2.23 REG0x23_Charger_Mask_0 Register (Address = 23h) [Reset = 00h]

REG0x23_Charger_Mask_0 is shown in Figure 8-37 and described in Table 8-29.

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Charger Mask 0

Figure 8-37 REG0x23_Charger_Mask_0 Register

7	6	5	4	3	2	1	0
RESERVED	ADC_DONE_MASK	TREG_MASK	VSYS_MASK	IINDPM_MASK	VINDPM_MASK	SAFETY_TMR_MASK	WD_MASK
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-29 REG0x23_Charger_Mask_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	ADC_DONE_MASK	R/W	0h	ADC conversion mask flag (only in one-shot mode) 0h = ADC conversion done does produce INT pulse 1h = ADC conversion done does not produce INT pulse
5	TREG_MASK	R/W	0h	IC thermal regulation mask flag 0h = Entering TREG does produce INT 1h = Entering TREG does not produce INT
4	VSYS_MASK	R/W	0h	VSYS min regulation mask flag 0h = Enter or exit VSYSMIN regulation does produce INT pulse 1h = Enter or exit VSYSMIN regulation does not produce INT pulse
3	IINDPM_MASK	R/W	0h	IINDPM or ILIM mask 0h = Enter IINDPM or ILIM does produce INT pulse 1h = Enter IINDPM or ILIM does not produce INT pulse
2	VINDPM_MASK	R/W	0h	VINDPM mask 0h = Enter VINDPM does produce INT pulse 1h = Enter VINDPM does not produce INT pulse
1	SAFETY_TMR_MASK	R/W	0h	Fast charge, trickle charge and pre-charge timer mask flag 0h = Fast charge, trickle charge or pre-charge timer expiration does produce INT 1h = Fast charge, trickle charge or pre-charge timer expiration does not produce INT
0	WD_MASK	R/W	0h	I2C watch dog timer mask 0h = I2C watch dog timer expired does produce INT pulse 1h = I2C watch dog timer expired does not produce INT pulse

8.6.2.24 REG0x24_Charger_Mask_1 Register (Address = 24h) [Reset = 00h]

REG0x24_Charger_Mask_1 is shown in Figure 8-38 and described in Table 8-30.

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Charger Mask 1

Figure 8-38 REG0x24_Charger_Mask_1 Register

7	6	5	4	3	2	1	0
RESERVED				CHG_MASK	RESERVED		VBUS_MASK
R-0h				R/W-0h	R-0h		R/W-0h

Table 8-30 REG0x24_Charger_Mask_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	CHG_MASK	R/W	0h	Charge status mask flag 0h = Charging status change does produce INT 1h = Charging status change does not produce INT
2:1	RESERVED	R	0h	Reserved
0	VBUS_MASK	R/W	0h	VBUS status mask flag 0h = VBUS status change does produce INT 1h = VBUS status change does not produce INT

8.6.2.25 REG0x25_FAULT_Mask_0 Register (Address = 25h) [Reset = 00h]

REG0x25_FAULT_Mask_0 is shown in Figure 8-39 and described in Table 8-31.

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FAULT Mask 0

Figure 8-39 REG0x25_FAULT_Mask_0 Register

7	6	5	4	3	2	1	0
VBUS_FAULT_MASK	BAT_FAULT_MASK	SYS_FAULT_MASK	RESERVED	TSHUT_MASK	RESERVED		TS_MASK
R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R-0h		R/W-0h

Table 8-31 REG0x25_FAULT_Mask_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VBUS_FAULT_MASK	R/W	0h	VBUS over-voltage and sleep comparator mask flag 0h = Entering VBUS OVP or sleep does produce INT 1h = Entering VBUS OVP or sleep does not produce INT
6	BAT_FAULT_MASK	R/W	0h	IBAT over current and VBAT overvoltage mask flag 0h = IBAT OCP fault or VBAT OVP fault does produce INT 1h = Neither IBAT OCP fault nor VBAT OVP fault produces INT
5	SYS_FAULT_MASK	R/W	0h	SYS over voltage and SYS short mask 0h = System over-voltage or SYS short fault does produce INT 1h = Neither system over voltage nor SYS short fault produces INT
4	RESERVED	R	0h	Reserved
3	TSHUT_MASK	R/W	0h	IC thermal shutdown mask flag 0h = TSHUT does produce INT 1h = TSHUT does not produce INT
2:1	RESERVED	R	0h
0	TS_MASK	R/W	0h	Temperature charging profile interrupt mask 0h = A change to TS temperature zone does produce INT 1h = A change to the TS temperature zone does not produce INT

8.6.2.26 REG0x26_ADC_Control Register (Address = 26h) [Reset = 30h]

REG0x26_ADC_Control is shown in Figure 8-40 and described in Table 8-32.

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ADC Control

Figure 8-40 REG0x26_ADC_Control Register

7	6	5	4	3	2	1	0
ADC_EN	ADC_RATE	ADC_SAMPLE		ADC_AVG	ADC_AVG_INIT	RESERVED
R/W-0h	R/W-0h	R/W-3h		R/W-0h	R/W-0h	R-0h

Table 8-32 REG0x26_ADC_Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ADC_EN	R/W	0h	ADC Control The registers POR to all 0 's, then after that always retain the last measurement, and never clear. 0h = Disable (default) 1h = Enable
6	ADC_RATE	R/W	0h	ADC conversion rate control 0h = Continuous conversion (default) 1h = One shot conversion
5:4	ADC_SAMPLE	R/W	3h	ADC sample speed 0h = 12 bit effective resolution 1h = 11 bit effective resolution 2h = 10 bit effective resolution 3h = 9 bit effective resolution (default)
3	ADC_AVG	R/W	0h	ADC average control 0h = Single value (default) 1h = Running average
2	ADC_AVG_INIT	R/W	0h	ADC average initial value control 0h = Start average using the existing register value (default) 1h = Start average using a new ADC conversion
1:0	RESERVED	R	0h	Reserved

8.6.2.27 REG0x27_ADC_Function_Disable_0 Register (Address = 27h) [Reset = 00h]

REG0x27_ADC_Function_Disable_0 is shown in Figure 8-41 and described in Table 8-33.

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ADC Function Disable 0

Figure 8-41 REG0x27_ADC_Function_Disable_0 Register

7	6	5	4	3	2	1	0
IBUS_ADC_DIS	IBAT_ADC_DIS	VBUS_ADC_DIS	VBAT_ADC_DIS	VSYS_ADC_DIS	TS_ADC_DIS	TDIE_ADC_DIS	VPMID_ADC_DIS
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-33 REG0x27_ADC_Function_Disable_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IBUS_ADC_DIS	R/W	0h	IBUS ADC control 0h = Enable (Default) 1h = Disable
6	IBAT_ADC_DIS	R/W	0h	IBAT ADC control 0h = Enable (Default) 1h = Disable
5	VBUS_ADC_DIS	R/W	0h	VBUS ADC control 0h = Enable (Default) 1h = Disable
4	VBAT_ADC_DIS	R/W	0h	VBAT ADC control 0h = Enable (Default) 1h = Disable
3	VSYS_ADC_DIS	R/W	0h	VSYS ADC control 0h = Enable (Default) 1h = Disable
2	TS_ADC_DIS	R/W	0h	TS ADC control 0h = Enable (Default) 1h = Disable
1	TDIE_ADC_DIS	R/W	0h	TDIE ADC control 0h = Enable (Default) 1h = Disable
0	VPMID_ADC_DIS	R/W	0h	VPMID ADC control 0h = Enable (Default) 1h = Disable

8.6.2.28 REG0x28_IBUS_ADC Register (Address = 28h) [Reset = 0000h]

REG0x28_IBUS_ADC is shown in Figure 8-42 and described in Table 8-34.

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IBUS ADC

Figure 8-42 REG0x28_IBUS_ADC Register

15	14	13	12	11	10	9	8
IBUS_ADC
R-0h

7	6	5	4	3	2	1	0
IBUS_ADC							RESERVED
R-0h							R-0h

Table 8-34 REG0x28_IBUS_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:1	IBUS_ADC	R	0h	IBUS ADC reading Reported in 2 's Complement. When the current is flowing from VBUS to PMID, IBUS ADC reports positive value, and when the current is flowing from PMID to VBUS, IBUS ADC reports negative value. POR: 0mA (0h) Format: 2s Complement Range: -4000mA-4000mA (7830h-7FFFh), (0h-7D0h) Clamped Low Clamped High Bit Step: 2mA
0	RESERVED	R	0h	Reserved

8.6.2.29 REG0x2A_IBAT_ADC Register (Address = 2Ah) [Reset = 0000h]

REG0x2A_IBAT_ADC is shown in Figure 8-43 and described in Table 8-35.

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IBAT ADC

Figure 8-43 REG0x2A_IBAT_ADC Register

15	14	13	12	11	10	9	8
IBAT_ADC
R-0h

7	6	5	4	3	2	1	0
IBAT_ADC						RESERVED
R-0h						R-0h

Table 8-35 REG0x2A_IBAT_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:2	IBAT_ADC	R	0h	IBAT ADC reading Reported in 2 's Complement. The IBAT ADC reports positive value for the battery charging current, and negative value for the battery discharging current. The IBAT ADC resets to zero when EN_CHG=0. POR: 0mA (0h) Format: 2s Complement Range: -7500mA-4000mA (38ADh-3FFFh), (0h-3E8h) Clamped Low Clamped High Bit Step: 4mA The IBAT ADC current can only be positive or zero in forward mode, and negative or zero in battery-only mode. If polarity of battery current changes from charging to discharging or vice-versa during the ADC measurement, the conversion is aborted and the register reports code 0x8000 (which is code 0x2000 for IBAT_ADC field)
1:0	RESERVED	R	0h	Reserved

8.6.2.30 REG0x2C_VBUS_ADC Register (Address = 2Ch) [Reset = 0000h]

REG0x2C_VBUS_ADC is shown in Figure 8-44 and described in Table 8-36.

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VBUS ADC

Figure 8-44 REG0x2C_VBUS_ADC Register

15	14	13	12	11	10	9	8
RESERVED	VBUS_ADC
R-0h	R-0h

7	6	5	4	3	2	1	0
VBUS_ADC						RESERVED
R-0h						R-0h

Table 8-36 REG0x2C_VBUS_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14:2	VBUS_ADC	R	0h	VBUS ADC reading POR: 0mV (0h) Range: 0mV-18000mV (0h-11B6h) Clamped High Bit Step: 3.97mV
1:0	RESERVED	R	0h	Reserved

8.6.2.31 REG0x2E_VPMID_ADC Register (Address = 2Eh) [Reset = 0000h]

REG0x2E_VPMID_ADC is shown in Figure 8-45 and described in Table 8-37.

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VPMID ADC

Figure 8-45 REG0x2E_VPMID_ADC Register

15	14	13	12	11	10	9	8
RESERVED	VPMID_ADC
R-0h	R-0h

7	6	5	4	3	2	1	0
VPMID_ADC						RESERVED
R-0h						R-0h

Table 8-37 REG0x2E_VPMID_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14:2	VPMID_ADC	R	0h	VPMID ADC reading POR: 0mV (0h) Range: 0mV-18000mV (0h-11B6h) Clamped High Bit Step: 3.97mV
1:0	RESERVED	R	0h	Reserved

8.6.2.32 REG0x30_VBAT_ADC Register (Address = 30h) [Reset = 0000h]

REG0x30_VBAT_ADC is shown in Figure 8-46 and described in Table 8-38.

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VBAT ADC

Figure 8-46 REG0x30_VBAT_ADC Register

15	14	13	12	11	10	9	8
RESERVED			VBAT_ADC
R-0h			R-0h

7	6	5	4	3	2	1	0
VBAT_ADC							RESERVED
R-0h							R-0h

Table 8-38 REG0x30_VBAT_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:13	RESERVED	R	0h	Reserved
12:1	VBAT_ADC	R	0h	VBAT ADC reading POR: 0mV (0h) Range: 0mV-5572mV (0h-AF0h) Clamped High Bit Step: 1.99mV
0	RESERVED	R	0h	Reserved

8.6.2.33 REG0x32_VSYS_ADC Register (Address = 32h) [Reset = 0000h]

REG0x32_VSYS_ADC is shown in Figure 8-47 and described in Table 8-39.

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VSYS ADC

Figure 8-47 REG0x32_VSYS_ADC Register

15	14	13	12	11	10	9	8
RESERVED			VSYS_ADC
R-0h			R-0h

7	6	5	4	3	2	1	0
VSYS_ADC							RESERVED
R-0h							R-0h

Table 8-39 REG0x32_VSYS_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:13	RESERVED	R	0h	Reserved
12:1	VSYS_ADC	R	0h	VSYS ADC reading POR: 0mV (0h) Range: 0mV-5572mV (0h-AF0h) Clamped High Bit Step: 1.99mV
0	RESERVED	R	0h	Reserved

8.6.2.34 REG0x34_TS_ADC Register (Address = 34h) [Reset = 0000h]

REG0x34_TS_ADC is shown in Figure 8-48 and described in Table 8-40.

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TS ADC

Figure 8-48 REG0x34_TS_ADC Register

15	14	13	12	11	10	9	8
RESERVED				TS_ADC
R-0h				R-0h

7	6	5	4	3	2	1	0
TS_ADC
R-0h

Table 8-40 REG0x34_TS_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0h	Reserved
11:0	TS_ADC	R	0h	TS ADC reading as TS pin voltage in percentage of bias reference. Valid with TS pin bias reference active. POR: 0%(0h) Range: 0% - 98.3103% (0h-3FFh) Clamped High Bit Step: 0.0961%

8.6.2.35 REG0x36_TDIE_ADC Register (Address = 36h) [Reset = 0000h]

REG0x36_TDIE_ADC is shown in Figure 8-49 and described in Table 8-41.

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TDIE ADC

Figure 8-49 REG0x36_TDIE_ADC Register

15	14	13	12	11	10	9	8
RESERVED				TDIE_ADC
R-0h				R-0h

7	6	5	4	3	2	1	0
TDIE_ADC
R-0h

Table 8-41 REG0x36_TDIE_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R	0h	Reserved
11:0	TDIE_ADC	R	0h	TDIE ADC reading Reported in 2 's Complement. POR: 0°C(0h) Format: 2s Complement Range: -40°C - 140°C (FB0h-118h) Clamped Low Clamped High Bit Step: 0.5°C

8.6.2.36 REG0x38_Part_Information Register (Address = 38h) [Reset = 02h]

REG0x38_Part_Information is shown in Figure 8-50 and described in Table 8-42.

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Part Information

Figure 8-50 REG0x38_Part_Information Register

7	6	5	4	3	2	1	0
RESERVED		PN			DEV_REV
R-0h		R-0h			R-2h

Table 8-42 REG0x38_Part_Information Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:3	PN	R	0h	Device Part number All the other options are reserved 3h = BQ25622E
2:0	DEV_REV	R	2h	Device Revision