JAJSD77A May   2017  – May 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 USB On-The-Go (OTG)
      4. 8.3.4 Converter Operation
        1. 8.3.4.1 Inductor Setting through IADPT Pin
        2. 8.3.4.2 Continuous Conduction Mode (CCM)
        3. 8.3.4.3 Pulse Frequency Modulation (PFM)
      5. 8.3.5 Current and Power Monitor
        1. 8.3.5.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.5.2 High-Accuracy Power Sense Amplifier (PSYS)
      6. 8.3.6 Input Source Dynamic Power Manage
      7. 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
      8. 8.3.8 Processor Hot Indication
        1. 8.3.8.1 PROCHOT During Low Power Mode
        2. 8.3.8.2 PROCHOT Status
      9. 8.3.9 Device Protection
        1. 8.3.9.1 Watchdog Timer
        2. 8.3.9.2 Input Overvoltage Protection (ACOV)
        3. 8.3.9.3 Input Overcurrent Protection (ACOC)
        4. 8.3.9.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.9.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.9.6 Battery Short
        7. 8.3.9.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
      2. 8.4.2 USB On-The-Go
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
          1. Table 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
          2. Table 8. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
        2. 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
          1. Table 9.  ChargeOption1 Register (SMBus address = 30h) Field Descriptions
          2. Table 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions
        3. 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
          1. Table 11. ChargeOption2 Register (SMBus address = 31h) Field Descriptions
          2. Table 12. ChargeOption2 Register (SMBus address = 31h) Field Descriptions
        4. 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
          1. Table 13. ChargeOption3 Register (SMBus address = 32h) Field Descriptions
          2. Table 14. ChargeOption3 Register (SMBus address = 32h) Field Descriptions
        5. 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
          1. Table 15. ProchotOption0 Register (SMBus address = 33h) Field Descriptions
          2. Table 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions
        6. 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
          1. Table 17. ProchotOption1 Register (SMBus address = 34h) Field Descriptions
          2. Table 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions
        7. 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
          1. Table 19. ADCOption Register (SMBus address = 35h) Field Descriptions
          2. Table 20. ADCOption Register (SMBus address = 35h) Field Descriptions
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
          1. Table 21. ChargerStatus Register (SMBus address = 20h) Field Descriptions
          2. Table 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions
        2. 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]
          1. Table 23. ProchotStatus Register (SMBus address = 21h) Field Descriptions
          2. Table 24. ProchotStatus Register (SMBus address = 21h) Field Descriptions
      3. 8.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
        1. Table 25. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions
        2. Table 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions
        3. 8.6.3.1   Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
        1. Table 27. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions
        2. Table 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions
      5. 8.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. Table 29. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions
        2. Table 30. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions
        3. 8.6.5.1   System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
            1. Table 31. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
            2. Table 32. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
            1. Table 33. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions
            2. Table 34. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions
          3. 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
            1. Table 35. InputVoltage Register (SMBus address = 3Dh) Field Descriptions
            2. Table 36. InputVoltage Register (SMBus address = 3Dh) Field Descriptions
      7. 8.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0h]
        1. Table 37. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
        2. Table 38. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
      8. 8.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0h]
        1. Table 39. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
        2. Table 40. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
      9. 8.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
        1. Table 41. ADCVBUS/PSYS Register Field Descriptions
      10. 8.6.10 ADCIBAT Register (SMBus address = 24h)
        1. Table 42. ADCIBAT Register Field Descriptions
      11. 8.6.11 ADCIINCMPIN Register (SMBus address = 25h)
        1. Table 43. ADCIINCMPIN Register Field Descriptions
      12. 8.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
        1. Table 44. ADCVSYSVBAT Register Field Descriptions
      13. 8.6.13 ID Registers
        1. 8.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
          1. Table 45. ManufactureID Register Field Descriptions
        2. 8.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
          1. Table 46. Device ID (DeviceAddress) Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1 SMBus Interface

The bq25700A device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq25700A device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq25700A device uses the SMBus read-word and write-word protocols (shown in Table 4 and Table 5) to communicate with the smart battery. The device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication starts when VCC is above V(UVLO).

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 15 and Figure 16 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq25700A supports the charger commands listed in Table 4.