JAJSD77A May   2017  – May 2018

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Up from Battery Without DC Source
      2. 8.3.2 Power-Up From DC Source
        1. 8.3.2.1 CHRG_OK Indicator
        2. 8.3.2.2 Input Voltage and Current Limit Setup
        3. 8.3.2.3 Battery Cell Configuration
        4. 8.3.2.4 Device Hi-Z State
      3. 8.3.3 USB On-The-Go (OTG)
      4. 8.3.4 Converter Operation
        1. 8.3.4.1 Inductor Setting through IADPT Pin
        2. 8.3.4.2 Continuous Conduction Mode (CCM)
        3. 8.3.4.3 Pulse Frequency Modulation (PFM)
      5. 8.3.5 Current and Power Monitor
        1. 8.3.5.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 8.3.5.2 High-Accuracy Power Sense Amplifier (PSYS)
      6. 8.3.6 Input Source Dynamic Power Manage
      7. 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)
      8. 8.3.8 Processor Hot Indication
        1. 8.3.8.1 PROCHOT During Low Power Mode
        2. 8.3.8.2 PROCHOT Status
      9. 8.3.9 Device Protection
        1. 8.3.9.1 Watchdog Timer
        2. 8.3.9.2 Input Overvoltage Protection (ACOV)
        3. 8.3.9.3 Input Overcurrent Protection (ACOC)
        4. 8.3.9.4 System Overvoltage Protection (SYSOVP)
        5. 8.3.9.5 Battery Overvoltage Protection (BATOVP)
        6. 8.3.9.6 Battery Short
        7. 8.3.9.7 Thermal Shutdown (TSHUT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forward Mode
        1. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 8.4.1.2 Battery Charging
      2. 8.4.2 USB On-The-Go
    5. 8.5 Programming
      1. 8.5.1 SMBus Interface
        1. 8.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 8.5.1.2 Timing Diagrams
    6. 8.6 Register Map
      1. 8.6.1  Setting Charge and PROCHOT Options
        1. 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
          1. Table 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
          2. Table 8. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
        2. 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]
          1. Table 9.  ChargeOption1 Register (SMBus address = 30h) Field Descriptions
          2. Table 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions
        3. 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]
          1. Table 11. ChargeOption2 Register (SMBus address = 31h) Field Descriptions
          2. Table 12. ChargeOption2 Register (SMBus address = 31h) Field Descriptions
        4. 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]
          1. Table 13. ChargeOption3 Register (SMBus address = 32h) Field Descriptions
          2. Table 14. ChargeOption3 Register (SMBus address = 32h) Field Descriptions
        5. 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]
          1. Table 15. ProchotOption0 Register (SMBus address = 33h) Field Descriptions
          2. Table 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions
        6. 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]
          1. Table 17. ProchotOption1 Register (SMBus address = 34h) Field Descriptions
          2. Table 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions
        7. 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
          1. Table 19. ADCOption Register (SMBus address = 35h) Field Descriptions
          2. Table 20. ADCOption Register (SMBus address = 35h) Field Descriptions
      2. 8.6.2  Charge and PROCHOT Status
        1. 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
          1. Table 21. ChargerStatus Register (SMBus address = 20h) Field Descriptions
          2. Table 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions
        2. 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]
          1. Table 23. ProchotStatus Register (SMBus address = 21h) Field Descriptions
          2. Table 24. ProchotStatus Register (SMBus address = 21h) Field Descriptions
      3. 8.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0h]
        1. Table 25. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions
        2. Table 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions
        3. 8.6.3.1   Battery Pre-Charge Current Clamp
      4. 8.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
        1. Table 27. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions
        2. Table 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions
      5. 8.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. Table 29. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions
        2. Table 30. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions
        3. 8.6.5.1   System Voltage Regulation
      6. 8.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 8.6.6.1 Input Current Registers
          1. 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]
            1. Table 31. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
            2. Table 32. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
          2. 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]
            1. Table 33. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions
            2. Table 34. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions
          3. 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
            1. Table 35. InputVoltage Register (SMBus address = 3Dh) Field Descriptions
            2. Table 36. InputVoltage Register (SMBus address = 3Dh) Field Descriptions
      7. 8.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0h]
        1. Table 37. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
        2. Table 38. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions
      8. 8.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0h]
        1. Table 39. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
        2. Table 40. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
      9. 8.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
        1. Table 41. ADCVBUS/PSYS Register Field Descriptions
      10. 8.6.10 ADCIBAT Register (SMBus address = 24h)
        1. Table 42. ADCIBAT Register Field Descriptions
      11. 8.6.11 ADCIINCMPIN Register (SMBus address = 25h)
        1. Table 43. ADCIINCMPIN Register Field Descriptions
      12. 8.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
        1. Table 44. ADCVSYSVBAT Register Field Descriptions
      13. 8.6.13 ID Registers
        1. 8.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
          1. Table 45. ManufactureID Register Field Descriptions
        2. 8.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
          1. Table 46. Device ID (DeviceAddress) Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ACP-ACN Input Filter
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Power MOSFETs Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Layout Consideration of Current Path
      2. 11.2.2 Layout Consideration of Short Circuit Protection
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RSN Package
32-Pin WQFN
Top View
bq25700A RSN.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
ACN 2 PWR Input current sense resistor negative input. The leakage on ACP and ACN are matched. The series resistors on the ACP and ACN pins are placed between sense resistor and filter cap. Refer to Application and Implementation for ACP/ACN filter design.
ACP 3 PWR Input current sense resistor positive input. The leakage on ACP and ACN are matched. The series resistors on the ACP and ACN pins are placed between sense resistor and filter cap. Refer to Application and Implementation for ACP/ACN filter design.
BATDRV 21 O P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on during fast charge and supplement mode.
BTST1 30 PWR Buck mode high side power MOSFET driver power supply. Connect a 0.047-µF capacitor between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.
BTST2 25 PWR Boost mode high side power MOSFET driver power supply. Connect a 0.047-μF capacitor between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.
CELL_BATPRESZ 18 I Battery cell selection pin for 1–4 cell battery setting. CELL_BATPRESZ pin is biased from VDDA. CELL_BATPRESZ pin also sets SYSOVP threshold to 5 V for 1-cell, 12 V for 2-cell, and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is pulled below VCELL_BATPRESZ_FALL to indicate battery removal. The device exits LEARN mode, and disables charge. REG0x15() goes back to default.
CHRG_OK 4 O Open drain active high indicator to inform the system good power source is connected to the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS is falls below 3.2 V or rises above 26 V, CHRG_OK is LOW. When fault occurs, CHRG_OK is asserted LOW.
CMPIN 14 I Input of independent comparator. The independent comparator compares the voltage sensed on CMPIN pin to internal reference, and its output is on CMPOUT pin. Internal reference, output polarity and deglitch time is selectable by SMBus. With polarity HIGH (REG0x30[6] = 1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity LOW (REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent comparator is not in use, tie CMPIN to ground.
CMPOUT 15 O Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup supply rail. Internal reference, output polarity and deglitch time are selectable by SMBus.
COMP2 17 I Buck boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 pin RC network.
COMP1 16 I Buck boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 pin RC network.
EN_OTG 5 I Active HIGH to enable OTG mode. When EN_OTG pin is HIGH and REG0x32[13] is HIGH, OTG can be enabled, refer to USB On-The-Go (OTG) for details of how to enable OTG function
HIDRV1 31 O Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET gate.
HIDRV2 24 O Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET gate.
IADPT 8 I/O Buffered adapter current output. V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)). With ratio selectable in REG0x12[4]. Place a resistor from the IADPT pin to ground corresponding to inductor in use. For 2.2 µH, the resistor is 137 kΩ. Place 100-pF or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.
IBAT 9 O Buffered battery current selected by SMBus. V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) for charge current, or V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable in REG0x12[3]. Place 100-pF or less ceramic decoupling capacitor from IBAT pin to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.
ILIM_HIZ 6 I Input current limit input. Program ILIM_HIZ voltage by connecting a resistor divider from supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM × RAC, in which IDPM is the target input current. The input current limit used by the charger is the lower setting of ILIM_HIZ pin and REG0x3F(). When the pin voltage is below 0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is above 0.8 V, the device is out of Hi-Z mode.
LODRV1 29 O Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET gate.
LODRV2 26 O Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET gate.
PGND 27 GND Device power ground.
PROCHOT 11 O Active low open drain output of processor hot indicator. It monitors adapter input current, battery discharge current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is asserted. The minimum pulse width is adjustable in REG0x33[5:2].
PSYS 10 O Current mode system power monitor. The output current is proportional to the total power from the adapter and battery. The gain is selectable through SMBus. Place a resistor from PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V. Place a capacitor in parallel with the resistor for filtering.
REGN 28 PWR 6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power ground. REGN pin output is for power stage gate drive.
SCL 13 I SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to SMBus specifications.
SDA 12 I/O SMBus open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to SMBus specifications.
SRN 19 PWR Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with optional 0.1-μF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and SRN.
SRP 20 PWR Charge current sense resistor positive input. Connect 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and SRN. Connect SRP pin with optional 0.1-uF ceramic capacitor to GND for common-mode filtering.
SW1 32 PWR Buck mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
SW2 23 PWR Boost mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
VBUS 1 PWR Charger input voltage. An input low pass filter of 1Ω and 0.47 µF (minimum) is recommended.
VDDA 7 PWR Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF ceramic capacitor from VDDA to power ground.
VSYS 22 PWR Charger system voltage sensing. The system voltage regulation limit is programmed in REG0x15() and REG0x3E().
Thermal pad – – Exposed pad beneath the IC. Analog ground and power ground star-connected near the IC's ground. Always solder thermal pad to the board, and have vias on the thermal pad plane connecting to power ground planes. It also serves as a thermal pad to dissipate the heat.