JAJSFQ9C june   2018  – may 2023 BQ25713 , BQ25713B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
        1. 9.5.1.1 Data Validity
        2. 9.5.1.2 START and STOP Conditions
        3. 9.5.1.3 Byte Format
        4. 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.5.1.5 Slave Address and Data Direction Bit
        6. 9.5.1.6 Single Read and Write
        7. 9.5.1.7 Multi-Read and Multi-Write
        8. 9.5.1.8 Write 2-Byte I2C Commands
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (I2C address = 31/30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (I2C address = 33/32h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (I2C address = 35/34h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (I2C address = 39/38h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (I2C address = 23/22h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0F/0Eh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (I2C address = 25/24h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (I2C address = 0B/0Ah) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (I2C address = 07/06h) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (I2C address = 09/08h) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (I2C address = 27/26h)
      10. 9.6.10 ADCIBAT Register (I2C address = 29/28h)
      11. 9.6.11 ADCIINCMPIN Register (I2C address = 2B/2Ah)
      12. 9.6.12 ADCVSYSVBAT Register (I2C address = 2D/2Ch)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (I2C address = 2Eh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = 0h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Timing Requirements

MINNOMMAXUNIT
I2C TIMING CHARACTERISTICS
trSCLK/SDATA rise time300ns
tfSCLK/SDATA fall time300ns
tW(H)SCLK pulse width high0.650µs
tW(L)SCLK Pulse Width Low1.3µs
tSU(STA)Setup time for START condition0.6µs
tH(STA)START condition hold time after which first clock pulse is generated0.6µs
tSU(DAT)Data setup time100ns
tH(DAT)Data hold time300ns
tSU(STOP)Setup time for STOP condition0.6µs
t(BUF)Bus free time between START and STOP condition1.3µs
FS(CL) Clock Frequency 10 400 kHz
HOST COMMUNICATION FAILURE
ttimeoutI2C bus release timeout(1)2535ms
tDeg_WDDeglitch for watchdog reset signal10ms
tWDIWatchdog timeout period, ChargeOption() bit [14:13] = 01(2)45.57s
Watchdog timeout period, ChargeOption() bit bit [14:13] = 10(2)7088105s
Watchdog timeout period, ChargeOption() bit bit [14:13] = 11(2)140175210s
(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).
(2) User can adjust threshold via I2C ChargeOption() REG0x01/00().