JAJSM11 may   2021 BQ25720

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Vmin Active Protection (VAP) with Battery only
      3. 9.3.3  Two-Level Battery Discharge Current Limit
      4. 9.3.4  Fast Role Swap Feature
      5. 9.3.5  CHRG_OK Indicator
      6. 9.3.6  Input and Charge Current Sensing
      7. 9.3.7  Input Voltage and Current Limit Setup
      8. 9.3.8  Battery Cell Configuration
      9. 9.3.9  Device HIZ State
      10. 9.3.10 USB On-The-Go (OTG)
      11. 9.3.11 Converter Operation
      12. 9.3.12 Inductance Detection Through IADPT Pin
      13. 9.3.13 Converter Compensation
      14. 9.3.14 Continuous Conduction Mode (CCM)
      15. 9.3.15 Pulse Frequency Modulation (PFM)
      16. 9.3.16 Switching Frequency and Dithering Feature
      17. 9.3.17 Current and Power Monitor
        1. 9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
      18. 9.3.18 Input Source Dynamic Power Management
      19. 9.3.19 Input Current Optimizer (ICO)
      20. 9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
      21. 9.3.21 Processor Hot Indication
        1. 9.3.21.1 PROCHOT During Low Power Mode
        2. 9.3.21.2 PROCHOT Status
      22. 9.3.22 Device Protection
        1. 9.3.22.1 Watchdog Timer
        2. 9.3.22.2 Input Overvoltage Protection (ACOV)
        3. 9.3.22.3 Input Overcurrent Protection (ACOC)
        4. 9.3.22.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.22.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.22.7 Battery Short Protection (BATSP)
        8. 9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 9.3.22.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.2.1 Battery Pre-Charge Current Clamp
      3. 9.6.3  ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (SMBus address = 21h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 22h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 9.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 9.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 9.6.10 ADCVSYSVBAT Register (SMBus address = 26h)
      11. 9.6.11 ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
      12. 9.6.12 ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
      19. 9.6.19 OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
      21. 9.6.21 InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      22. 9.6.22 VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
      23. 9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
      24. 9.6.24 ID Registers
        1. 9.6.24.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.24.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.3 Application Curves

GUID-0F546B48-F97F-47B3-B843-95D9424D10ED-low.gif
2-cell without battery
Figure 10-3 Power Up From 20 V
GUID-987B2618-DAD5-4620-8762-60C36633A96D-low.gif
3-cell VBAT = 10 V
Figure 10-5 Power Off From 12 V
GUID-99BABC0F-79E2-431C-BD01-831417DD23D5-low.gif
VBUS = 20 V, VSYS = 10 V, ISYS = 200 mA
Figure 10-7 PFM Operation
GUID-D605425B-21BD-491A-ADC1-30E044BC02FA-low.gif
VBUS = 5 V, VBAT = 10 V
Figure 10-9 Switching During Boost Mode
GUID-AAAC6199-B8E7-4BCB-AED4-D38927F4FA9E-low.gif
VBUS = 12 V/3.25 A, 3-cell, VSYS = 9 V, Without battery
Figure 10-11 System Regulation in Buck Mode
GUID-B2809831-C0EB-4F40-BEB6-7CD6E7DB0921-low.gif
VBUS = 5 V/3.25 A, 3-cell, VSYS = 9 V, Without battery
Figure 10-13 System Regulation in Boost Mode
GUID-DF5637EF-9FBF-4AE8-817C-C6F0C3C2E749-low.gif
VBUS = 5 V/3.25 A, VBAT = 7.5 V
Figure 10-15 Input Current in Boost Mode
GUID-F7522687-2A8F-444A-8272-DC145310AB11-low.gif
VBAT = 10 V, VBUS 5 V to 20 V, IOTG = 500 mA
Figure 10-17 OTG Voltage Ramp Up
GUID-29350701-0368-493A-8D1C-8157BAD7EC70-low.gif
VBAT = 10 V, VBUS = 20 V
Figure 10-19 OTG Load Transient
GUID-20201002-CA0I-XVFK-SLPG-WMNQKPHRHQCZ-low.gif
VBUS = 20 V IIN_DPM = 2 A ILIM2_VTH = 200%
TMAX = 20 ms TOVLD = 10 ms VSYS_MIN = 12.3 V
ISYS = 1 to 6 A ICHG = 0 A
Figure 10-21 Peak Power Mode VSYS Trigger
GUID-C8A099E7-4926-4CB7-B749-2F6974316A4E-low.gif
2-cell without battery
Figure 10-4 Power Up From 5 V
GUID-5A364211-3434-4FC4-AD21-F6CB5513EB28-low.gif
VBUS 5 V to 20 V
Figure 10-6 Line Regulation
GUID-24BA0D66-2CCA-4385-8DF0-332D0B391D3E-low.gif
VBUS = 20 V, VSYS = 10 V, ISYS = 2 A
Figure 10-8 PWM Operation
GUID-BFD0BED4-1F08-44C3-B5E7-E879485D70A5-low.gif
VBUS = 12 V, VBAT = 12 V
Figure 10-10 Switching During Buck Boost Mode
GUID-F3E6E4A9-A7B2-4BBE-8BBD-11DC86E510E3-low.gif
VBUS = 9 V/3.25 A, 3-cell, VSYS = 9 V, Without battery
Figure 10-12 System Regulation in Buck Boost Mode
GUID-99137B28-2BB6-4CC7-B02B-0F8B1978373B-low.gif
VBUS = 20 V/3.25 A, VBAT = 7.5 V
Figure 10-14 Input Current Regulation in Buck Mode
GUID-349BE387-9AD4-4CB8-9C8A-24B4D8A5AAC7-low.gif
VBUS = 5 V
Figure 10-16 OTG Power Up from 8-V Battery
GUID-8F30EAC9-29F1-4C03-8AC2-18CF6221F285-low.gif
Figure 10-18 OTG Power Off
GUID-20200921-CA0I-QVN6-DNLK-ZRWHQ4SW6FZV-low.gif
VBUS = 20 V, VOTG = 5 V, ISYS = 5 A,VBAT = 14.8 V
Figure 10-20 FRS Transition Waveform
GUID-20201002-CA0I-HQPB-HWW8-WRKPWDGFT9NX-low.gif
VBUS = 20 V IIN_DPM = 2 A ILIM2_VTH = 200%
TMAX = 20 ms TOVLD = 10 ms VBAT = 12.8 V
ISYS = 1 to 6 A ICHG = 0 A
Figure 10-22 Peak Power Mode IBUS Trigger