JAJSL70A
February 2021 – January 2024
BQ25730
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
概要 (続き)
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics(BQ25730)
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Power-Up Sequence
8.3.2
Two-Level Battery Discharge Current Limit
8.3.3
Fast Role Swap Feature
8.3.4
CHRG_OK Indicator
8.3.5
Input and Charge Current Sensing
8.3.6
Input Voltage and Current Limit Setup
8.3.7
Battery Cell Configuration
8.3.8
Device HIZ State
8.3.9
USB On-The-Go (OTG)
8.3.10
Converter Operation
8.3.11
Inductance Detection Through IADPT Pin
8.3.12
Converter Compensation
8.3.13
Continuous Conduction Mode (CCM)
8.3.14
Pulse Frequency Modulation (PFM)
8.3.15
Switching Frequency and Dithering Feature
8.3.16
Current and Power Monitor
8.3.16.1
High-Accuracy Current Sense Amplifier (IADPT and IBAT)
8.3.16.2
High-Accuracy Power Sense Amplifier (PSYS)
8.3.17
Input Source Dynamic Power Management
8.3.18
Input Current Optimizer (ICO)
8.3.19
Two-Level Adapter Current Limit (Peak Power Mode)
8.3.20
Processor Hot Indication
8.3.20.1
PROCHOT During Low Power Mode
8.3.20.2
PROCHOT Status
8.3.21
Device Protection
8.3.21.1
Watchdog Timer
8.3.21.2
Input Overvoltage Protection (ACOV)
8.3.21.3
Input Overcurrent Protection (ACOC)
8.3.21.4
System Overvoltage Protection (SYSOVP)
8.3.21.5
Battery Overvoltage Protection (BATOVP)
8.3.21.6
Battery Discharge Overcurrent Protection (BATOC)
8.3.21.7
Battery Short Protection (BATSP)
8.3.21.8
System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
8.3.21.9
Thermal Shutdown (TSHUT)
8.4
Device Functional Modes
8.4.1
Forward Mode
8.4.1.1
System Voltage Regulation with Narrow VDC Architecture
8.4.1.2
Battery Charging
8.4.2
USB On-The-Go
8.4.3
Pass Through Mode (PTM)-Patented Technology
8.5
Programming
8.5.1
I2C Serial Interface
8.5.1.1
Timing Diagrams
8.5.1.2
Data Validity
8.5.1.3
START and STOP Conditions
8.5.1.4
Byte Format
8.5.1.5
Acknowledge (ACK) and Not Acknowledge (NACK)
8.5.1.6
Target Address and Data Direction Bit
8.5.1.7
Single Read and Write
8.5.1.8
Multi-Read and Multi-Write
8.5.1.9
Write 2-Byte I2C Commands
8.6
Register Map
8.6.1
ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
8.6.2
ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
8.6.2.1
Battery Pre-Charge Current Clamp
8.6.3
ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
8.6.4
ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
8.6.5
ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
8.6.6
IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
8.6.7
ADCVBUS/PSYS Register (I2C address = 27/26h)
8.6.8
ADCIBAT Register (I2C address = 29/28h)
8.6.9
ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
8.6.10
ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
8.6.11
ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]
8.6.12
ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
8.6.13
ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
8.6.14
ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
8.6.15
ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
8.6.16
ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
8.6.17
ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
8.6.18
Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
8.6.19
OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
8.6.20
OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
8.6.21
InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
8.6.22
VSYS_MIN Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
8.6.23
IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]
8.6.24
ID Registers
8.6.24.1
ManufactureID Register (I2C address = 2Eh) [reset = 40h]
8.6.24.2
Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D5h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Input Snubber and Filter for Voltage Spike Damping
9.2.2.2
ACP-ACN Input Filter
9.2.2.3
Inductor Selection
9.2.2.4
Input Capacitor
9.2.2.5
Output Capacitor
9.2.2.6
Power MOSFETs Selection
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.2.1
Layout Example Reference Top View
11.2.2
Inner Layer Layout and Routing Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
サード・パーティ製品に関する免責事項
12.2
Documentation Support
12.2.1
Related Documentation
12.3
ドキュメントの更新通知を受け取る方法
12.4
サポート・リソース
12.5
Trademarks
12.6
静電気放電に関する注意事項
12.7
用語集
13
Revision History
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RSN|32
MPQF194B
サーマルパッド・メカニカル・データ
RSN|32
QFND189E
発注情報
jajsl70a_oa
jajsl70a_pm
7
Specifications