JAJSL33A june 2020 – january 2021 BQ25731
PRODUCTION DATA
CELL_BATPRESZ pin is biased with a resistor divider from VDDA to GND. After REGN LDO is activated (VDDA rise up), the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. No external cap is allowed at CELL_BATPRESZ pin. When CELL_BATPRESZ pin is pulled down to GND (because of battery removal) at the beginning of startup process, VSYS_MIN = 3.6 V and SYS_OVP = 25 V and Maximum charge voltage (REG0x15) follow 1 cell default setting 4.2 V. VSYS and VBAT ADC offset is also determined by CELL_BATPRESZ pin setting, under 1S-4S VSYS/VBAT ADC holds 2.88-V offset, however under 5S detection VSYS/VBAT ADC only holds 8.16-V offset to cover higher voltage range. Refer to Table 9-2 for CELL_BATPRESZ pin configuration typical voltage for swept cell count.
CELL COUNT | PIN VOLTAGE w.r.t. VDDA | CHARGEVOLTAGE (REG0x05/04h) | SYSOVP | VSYS_MIN | VSYS/VBAT ADC OFFSET |
---|---|---|---|---|---|
5S | 100%(Directly connect to VDDA) | 21.000 V | 25 V | 15.4 V | 8.16 V |
4S | 75% | 16.800 V | 19.5 V | 12.3 V | 2.88 V |
3S | 55% | 12.600 V | 19.5 V | 9.2 V | 2.88 V |
2S | 40% | 8.400 V | 12 V | 6.6 V | 2.88 V |
1S | 25% | 4.200 V | 6 V | 3.6 V | 2.88 V |
Battery removal | 0% | 4.200 V | 25 V | 3.6 V | 2.88 V |