JAJSL33A june   2020  – january 2021 BQ25731

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics(BQ25731)
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Two-Level Battery Discharge Current Limit
      3. 9.3.3  Fast Role Swap Feature
      4. 9.3.4  CHRG_OK Indicator
      5. 9.3.5  Input and Charge Current Sensing
      6. 9.3.6  Input Voltage and Current Limit Setup
      7. 9.3.7  Battery Cell Configuration
      8. 9.3.8  Device HIZ State
      9. 9.3.9  USB On-The-Go (OTG)
      10. 9.3.10 Converter Operation
      11. 9.3.11 Inductance Detection Through IADPT Pin
      12. 9.3.12 Converter Compensation
      13. 9.3.13 Continuous Conduction Mode (CCM)
      14. 9.3.14 Pulse Frequency Modulation (PFM)
      15. 9.3.15 Switching Frequency and Dithering Feature
      16. 9.3.16 Current and Power Monitor
        1. 9.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)
      17. 9.3.17 Input Source Dynamic Power Management
      18. 9.3.18 Input Current Optimizer (ICO)
      19. 9.3.19 Two-Level Adapter Current Limit (Peak Power Mode)
      20. 9.3.20 Processor Hot Indication
        1. 9.3.20.1 PROCHOT During Low Power Mode
        2. 9.3.20.2 PROCHOT Status
      21. 9.3.21 Device Protection
        1. 9.3.21.1 Watchdog Timer
        2. 9.3.21.2 Input Overvoltage Protection (ACOV)
        3. 9.3.21.3 Input Overcurrent Protection (ACOC)
        4. 9.3.21.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.21.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.21.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.21.7 Battery Short Protection (BATSP)
        8. 9.3.21.8 System Undervoltage Lockout (VSYS_UVP)
        9. 9.3.21.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
        1. 9.5.1.1 Timing Diagrams
        2. 9.5.1.2 Data Validity
        3. 9.5.1.3 START and STOP Conditions
        4. 9.5.1.4 Byte Format
        5. 9.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 9.5.1.6 Target Address and Data Direction Bit
        7. 9.5.1.7 Single Read and Write
        8. 9.5.1.8 Multi-Read and Multi-Write
        9. 9.5.1.9 Write 2-Byte I2C Commands
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (I2C address = 03/02h) [reset = 0080h]
        1. 9.6.2.1 Battery Low Voltage Current Clamp
      3. 9.6.3  ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (I2C address = 27/26h)
      8. 9.6.8  ADCIBAT Register (I2C address = 29/28h)
      9. 9.6.9  ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
      10. 9.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
      11. 9.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]
      12. 9.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
      19. 9.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
      21. 9.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
      22. 9.6.22 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]
      23. 9.6.23 ID Registers
        1. 9.6.23.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
        2. 9.6.23.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D6h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 10.2.2.2 ACP-ACN Input Filter
        3. 10.2.2.3 Inductor Selection
        4. 10.2.2.4 Input Capacitor
        5. 10.2.2.5 Output Capacitor
        6. 10.2.2.6 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]

To set the VAP VBUS PROCHOT trigger threshold, write a 7-bit Vmin Active Protection register command (REG0x3F[7:1]) using the data format listed in Figure 9-33 and Table 9-42. The charger provides VAP mode VBUS PROCHOT trigger threshold range from 3.2 V (0000000b) to 15.9 V (1111111b), with 100-mV step resolution. There is a fixed offset of 3.2 V. Upon POR, the VBUS PROCHOT trigger threshold is 3.2 V (0000000b).

To set VSYS_TH2 Threshold to assert STAT_VSYS, write a 6-bit Vmin Active Protection register command (REG0x3E[7:2]) using the data format listed in Figure 9-33 and Table 9-43. The charger Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is below the thresholds. The threshold range from 3.2 V (000000b) to 9.5 V (111111b) for 2s~5s and 3.2 V (000000b) to 3.9 V (000111b) for 1S, with 100-mV step resolution. There is a fixed DC offset which is 3.2 V. Under 1S application writing beyond 3.9 V will be ignored. For example, xxx111b and 000111b result in same VSYS_TH2 setting 3.9 V. Upon POR, the VSYS PROCHOT trigger threshold is 3.2 V (000000b) for 1S and 5.9 V (011011b) for 2s~5s .

Figure 9-33 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 0070h/0004h]
7 6 5 4 3 2 1 0
VBUS_VAP_TH Bit6 VBUS_VAP_TH Bit5 VBUS_VAP_TH Bit4 VBUS_VAP_TH Bit3 VBUS_VAP_TH Bit2 VBUS_VAP_TH Bit1 VBUS_VAP_TH Bit0 Reserved
R/W R/W
7 6 5 4 3 2 1 0
VSYS_TH2 Bit6 VSYS_TH2 Bit5 VSYS_TH2 Bit4 VSYS_TH2 Bit3 VSYS_TH2 Bit2 VSYS_TH2 Bit1 EN_TH2_FOLLOW_TH1 EN_FRS
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-42 Vmin Active Protection Register (I2C address = 3Fh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 VBUS_VAP_TH, Bit6 R/W 0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 6400 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
6 VBUS_VAP_TH, Bit5 R/W 0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 3200 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
5 VBUS_VAP_TH, Bit4 R/W 0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 1600 mV of VAP Mode VBUS PROCHOT trigger voltage threshold
4 VBUS_VAP_TH, Bit3 R/W 0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 800 mV of VAP mode VBUS PROCHOT trigger voltage threshold
3 VBUS_VAP_TH, Bit2 R/W 0b

0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold

1 = Adds 400 mV of VAP mode VBUS PROCHOT trigger voltage threshold
2 VBUS_VAP_TH, Bit1 R/W 0b

0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold

1 = Adds 200 mV of VAP mode VBUS PROCHOT trigger voltage threshold
1 VBUS_VAP_TH, Bit0 R/W 0b

0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold

1 = Adds 100 mV of VAP mode VBUS PROCHOT trigger voltage threshold
0 Reserve R/W 0b Reserve
Table 9-43 Vmin Active Protection Register (I2C address = 3Eh) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 VSYS_TH2, Bit5 R/W 0b

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 3200 mV of VAP mode VSYS PROCHOT trigger voltage threshold
6 VSYS_TH2, Bit4 R/W

1b(2S~5s)

0b(1S)

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 1600 mV of VAP mode VSYS PROCHOT trigger voltage threshold
5 VSYS_TH2, Bit3 R/W

1b(2S~5s)

0b(1S)

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 800 mV of VAP mode VSYS PROCHOT trigger voltage threshold
4 VSYS_TH2, Bit2 R/W

0b

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 400 mV of VAP mode VSYS PROCHOT trigger voltage threshold
3 VSYS_TH2, Bit1 R/W 0b(1S)

1b(2S~5s)

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 200 mV of VAP mode VSYS PROCHOT trigger voltage threshold
2 VSYS_TH2, Bit0 R/W

1b

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 100 mV of VAP mode VSYS PROCHOT trigger voltage threshold
1 EN_VSYSTH2_FOLLOW_VSYSTH1 R/W 0b

Enable internal VSYS_TH2 follow VSYS_TH1 setting neglecting register REG37[7:2] setting

0b: disable <default at POR>

1b: enable
0 EN_FRS R/W 0b

Fast Role Swap feature enable (note not recommend to change EN_FRS during OTG operation, the FRS bit from 0 to 1 change will disable power stage for about 200 μs (Fs = 400 kHz). HIZ mode holds higher priority, If EN_HIZ=1b, this EN_FRS bit should be forced to 0b.

0b: disable <default at POR>

1b: enable