JAJSL33A june 2020 – january 2021 BQ25731
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PKPWR_TOVLD_DEG | EN_PKPWR_IIN_DPM | EN_PKPWR_VSYS | PKPWR_OVLD_STAT | PKPWR_RELAX_STAT | PKPWR_TMAX[1:0] | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN_EXTILIM | EN_ICHG_IDCHG | Q2_OCP | ACX_OCP | EN_ACOC | ACOC_VTH | EN_BATOC | BATOC_VTH |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7-6 | PKPWR_TOVLD_DEG | R/W | 00b | Input Overload time in Peak Power Mode 00b: 1 ms <default at POR> 01b: 2 ms 10b: 5 ms 11b: 10 ms |
| 5 | EN_PKPWR_IIN_DPM | R/W | 0b | Enable Peak Power Mode triggered by input current overshoot If REG0x33[5:4] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b. 0b: Disable peak power mode triggered by input current overshoot <default at POR> 1b: Enable peak power mode triggered by input current overshoot. |
| 4 | EN_PKPWR_VSYS | R/W | 0b | Enable Peak Power Mode triggered by system voltage under-shoot If REG0x33[5:4] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b. 0b: Disable peak power mode triggered by system voltage under-shoot <default at POR> 1b: Enable peak power mode triggered by system voltage under-shoot. |
| 3 | STAT_PKPWR_OVLD | R/W | 0b | Indicator that the device is in overloading cycle. Write 0 to get out of overloading cycle. 0b: Not in peak power mode. <default at POR> 1b: In peak power mode. |
| 2 | STAT_PKPWR_RELAX | R/W | 0b | Indicator that the device is in relaxation cycle. Write 0 to get out of relaxation cycle. 0b: Not in relaxation cycle. <default at POR> 1b: In relaxation mode. |
| 1-0 | PKPWR_TMAX[1:0] | R/W | 00b | Peak power mode overload and relax cycle time. 00b: 20 ms <default at POR> 01b: 40 ms 10b: 80 ms 11b: 1 sec |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | EN_EXTILIM | R/W | 1b | Enable ILIM_HIZ pin to set input current limit 0b: Input current limit is set by IIN_DPM register.. 1b: Input current limit is set by the lower value of ILIM_HIZ pin and IIN_DPM register.. <default at POR> |
| 6 | EN_ICHG_IDCHG | R/W | 0b | 0b: IBAT pin as discharge current. <default at POR> 1b: IBAT pin as charge current. |
| 5 | Q2_OCP | R/W | 1b | Q2 OCP threshold by sensing Q2 VDS 0b: 210 mV 1b: 150 mV <default at POR> |
| 4 | ACX_OCP | R/W | 1b | Fixed Input current OCP threshold by sensing ACP-ACN, converter is disabled immediately when triggered non latch protection resume switching automatically after ACX comparator release. 0b: 280 mV(RSNS_RAC=0b)/200 mV(RSNS_RAC=1b) 1b: 150 mV(RSNS_RAC=0b)/100 mV(RSNS_RAC=1b) <default at POR> |
| 3 | EN_ACOC | R/W | 0b | ACOC Enable Configurable Input overcurrent (ACOC) protection by sensing the voltage across ACP and ACN. Upon ACOC (after 250-μs blank-out time), converter is disabled. Non latch fault, after 250-ms falling edge de-glitch time converter starts switching automatically. 0b: Disable ACOC <default at POR> 1b: ACOC threshold 133% or 200% ILIM2 |
| 2 | ACOC_VTH | R/W | 1b | ACOC Limit Set MOSFET OCP threshold as percentage of IIN_DPM with current sensed from RAC. 0b: 133% of ILIM2 1b: 200% of ILIM2 <default at POR> |
| 1 | EN_BATOC | R/W | 1b | BATOC Battery discharge overcurrent (BATOC) protection by sensing the voltage across SRN and SRP. Upon BATOC, converter is disabled. 0b: Disable BATOC 1b: Enable BATOC threshold 133% or 200% PROCHOT IDCHG_TH2 <default at POR> |
| 0 | BATOC_VTH | R/W | 1b | Set battery discharge overcurrent threshold as percentage of PROCHOT battery discharge current limit. Note when SRN and SRP common voltage is low for 1S application, the BATOC threshold could be derating. 0b: 133% of PROCHOT IDCHG_TH2 1b: 200% of PROCHOT IDCHG _TH2<default at POR> |