JAJSSE4 December   2023 BQ25750

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics (BQ25750)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power-On-Reset
      2. 8.3.2 Device Power-Up From Battery Without Input Source
      3. 8.3.3 Device Power Up from Input Source
        1. 8.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 8.3.3.2 REGN Regulator (REGN LDO)
        3. 8.3.3.3 Compensation-Free Buck-Boost Converter Operation
          1. 8.3.3.3.1 Light-Load Operation
        4. 8.3.3.4 Switching Frequency and Synchronization (FSW_SYNC)
        5. 8.3.3.5 Device HIZ Mode
      4. 8.3.4 Battery Charging Management
        1. 8.3.4.1 Autonomous Charging Cycle
          1. 8.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 8.3.4.2 Li-Ion Battery Charging Profile
        3. 8.3.4.3 LiFePO4 Battery Charging Profile
        4. 8.3.4.4 Charging Termination for Li-ion and LiFePO4
        5. 8.3.4.5 Charging Safety Timer
        6. 8.3.4.6 Thermistor Qualification
          1. 8.3.4.6.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.4.6.2 Cold/Hot Temperature Window in Reverse Mode
      5. 8.3.5 Power Path Management
        1. 8.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 8.3.5.1.1 Input Current Regulation
            1. 8.3.5.1.1.1 ILIM_HIZ Pin
          2. 8.3.5.1.2 Input Voltage Regulation
            1. 8.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 8.3.6 Reverse Mode Power Direction
        1. 8.3.6.1 Auto Reverse Mode
      7. 8.3.7 Integrated 16-Bit ADC for Monitoring
      8. 8.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
        1. 8.3.8.1 Power Good Indicator (PG)
        2. 8.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 8.3.8.3 Interrupt to Host (INT)
      9. 8.3.9 Serial Interface
        1. 8.3.9.1 Data Validity
        2. 8.3.9.2 START and STOP Conditions
        3. 8.3.9.3 Byte Format
        4. 8.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.9.5 Target Address and Data Direction Bit
        6. 8.3.9.6 Single Write and Read
        7. 8.3.9.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 BQ25750 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  ACUV / ACOV Input Voltage Operating Window Programming
          2. 9.2.1.2.2  Charge Voltage Selection
          3. 9.2.1.2.3  Switching Frequency Selection
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Input (VAC / SYS) Capacitor
          6. 9.2.1.2.6  Output (VBAT) Capacitor
          7. 9.2.1.2.7  Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 9.2.1.2.8  Power MOSFETs Selection
          9. 9.2.1.2.9  ACFETs and BATFETs Selection
          10. 9.2.1.2.10 Converter Fast Transient Response
        3. 9.2.1.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.2.1.2.6 Output (VBAT) Capacitor

In forward boost mode or reverse buck mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is given by where the minimum VAC corresponds to the maximum capacitor current.

Equation 15. I C B A T = I B A T V B A T V A C - 1

In this case, the highest ripple occurs with highest VBAT and lowest VAC: I C B A T = 10 A 58 V 40 V - 1 = 6.9 A . A 5-mΩ output capacitor ESR causes an output voltage ripple of 74 mV as given by:

Equation 16. ΔVRIPPLE(ESR)=IBAT×VBATVAC,min×ESR

A 140-μF output capacitor causes a capacitive ripple voltage of 66 mV as given by:

Equation 17. Δ V R I P P L E ( C B A T ) = I B A T × 1 - V A C , m i n V B A T C B A T × f S W

A combination of ceramic and bulk capacitors should be used to provide low ESR and high ripple current capacity. Ceramic capacitors should be placed close to the switching half-bridge. Given total bulk output capacitance, it is recommended to distribute equally on either side of RBAT_SNS. The complete schematic is a good starting point for CBAT for typical applications.