JAJSVD8 August 2024 BQ25758A
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The device can be configured as buck-only using the MODE pin as described in MODE Pin Configuration section. In this mode, the Q3 and Q4 FETs must be removed from the system. Please see the diagram below showing buck-only mode without the boost FETs Q3 and Q4. An optional gate drive voltage can be provided using the DRV_SUP pin to reduce switching losses. Figure 8-25 shows a typical schematic when using the device as a buck with 48-V input, configurable output voltage for USB-PD EPR and 5-A output current.
COMPONENT | VALUE | RECOMMENDED PART NO. |
---|---|---|
Q1, Q2 | 80 V, 6.2 mΩ | SiR880BDP |
L1 | 10 μH, 22 mΩ | CMLB135T-100MS |