JAJSVD8 August 2024 BQ25758A
PRODUCTION DATA
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PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
QUIESCENT CURRENTS | ||||||
IQ_VAC | Quiescent input current (IVAC) | Not switching | 0.75 | 1 | mA | |
IQ_REV | Quiescent battery current in Reverse mode (ISRN + ISRP) | Not switching | 0.75 | 1 | mA | |
VAC / BAT POWER UP | ||||||
VVAC_OP | VAC operating range | 4.4 | 60 | V | ||
VVAC_OK | VAC converter enable threshold | VAC rising, no battery | 4.4 | V | ||
VVAC_OKZ | VAC converter disable threshold | VAC falling, no battery | 3.5 | V | ||
VREF_ACUV | ACUV comparator threshold to enter VAC_UVP | VACUV falling | 1.095 | 1.1 | 1.106 | V |
VREF_ACUV_HYS | ACUV comparator threshold hysteresis | VACUV rising | 50 | mV | ||
VVAC_INT_OV | VAC internal threshold to enter VAC_OVP | IN rising | 66 | V | ||
VVAC_INT_OVZ | VAC internal thresholds to exit VAC_OVP | IN falling | 63 | V | ||
VREF_ACOV | ACOV comparator threshold to enter VAC_OVP | VACOV rising | 1.184 | 1.2 | 1.206 | V |
VREF_ACOV_HYS | ACOV comparator threshold hysteresis | VACOV falling | 50 | mV | ||
OUTPUT VOLTAGE REGULATION | ||||||
VOUT_REG_RANGE | Output voltage regulation range | 3.3 | 60 | V | ||
VOUT_REG_ACC | I2C setting output voltage regulation accuracy | VOUT_REG = 0x0960 | 48 | V | ||
-2 | 2 | % | ||||
VOUT_REG = 0x0578 | 28 | V | ||||
-2 | 2 | % | ||||
VOUT_REG_ACC | I2C setting output voltage regulation accuracy | VOUT_REG = 0x02EE | 15 | V | ||
-2 | 2 | % | ||||
VOUT_REG = 0x00FA | 5 | V | ||||
-2 | 2 | % | ||||
OUTPUT CURRENT REGULATION | ||||||
IOUT_REG_RANGE | Output current regulation range | 0.4 | 20 | A | ||
IOUT_REG_ACC | I2C setting output current regulation accuracy | ROUT_SNS = 5mΩ, VOUT = 12V. IOUT_REG = 0x012C | 15 | A | ||
–3 | 3 | % | ||||
ROUT_SNS = 5mΩ, VOUT = 12V. IOUT_REG = 0x0064 | 5 | A | ||||
–3 | 3 | % | ||||
ROUT_SNS = 5mΩ, VOUT = 12V. IOUT_REG = 0x0028 | 2 | A | ||||
–5 | 5 | % | ||||
KIOUT | Hardware output current limit set factor (Amperes of output current per kΩ on IOUT pin) | ROUT_SNS = 5mΩ, RIOUT = 10kΩ, 5kΩ, and 3.33kΩ | 48 | 50 | 52 | A x kΩ |
VREF_IOUT | IOUT pin voltage when IOUT pin is in regulation | 2.0 | V | |||
INPUT CURRENT REGULATION | ||||||
IIREG_DPM_ACC | I2C setting input current regulation accuracy in forward mode | RAC_SNS = 5mΩ, IAC_DPM = 0x00A0 | 8 | A | ||
–3 | 3 | % | ||||
RAC_SNS = 5mΩ, IAC_DPM = 0x0050 | 4 | A | ||||
–4 | 4 | % | ||||
RAC_SNS = 5mΩ, IAC_DPM = 0x0028 | 2 | A | ||||
–7 | 7 | % | ||||
KILIM | Hardware input current limit set factor (Amperes of input current per kΩ on ILIM_HIZ pin) | RAC_SNS = 5mΩ, RILIM = 5kΩ, 2.5kΩ, and 1.67kΩ | 19.2 | 20 | 20.8 | A x kΩ |
VREF_ILIM_HIZ | ILIM_HIZ pin voltage when ILIM_HIZ pin is in regulation | 2.0 | V | |||
VIH_ILIM_HIZ | ILIM_HIZ input high threshold to enter HIZ mode | VILIM_HIZ rising | 3.7 | V | ||
INPUT VOLTAGE REGULATION | ||||||
VVREG_DPM_RANGE | Input voltage DPM regulation range | 4.4 | 60 | V | ||
VVREG_DPM_ACC | I2C setting input voltage regulation accuracy | VAC_DPM = 0x076C | 38 | V | ||
–2 | 2 | % | ||||
VVREG_DPM_ACC | I2C setting input voltage regulation accuracy in forward mode | VAC_DPM = 0x04E2 | 25 | V | ||
–2 | 2 | % | ||||
VAC_DPM = 0x03B6 | 19 | V | ||||
–2 | 2 | % | ||||
VACUV_DPM | ACUV pin voltage when in VDPM regulation | 1.198 | 1.210 | 1.222 | V | |
REVERSE MODE VOLTAGE REGULATION | ||||||
VREV_RANGE | VAC Voltage regulation range in Reverse mode | 3.3 | 60 | V | ||
VREV_ACC | Voltage regulation accuracy in Reverse mode | VAC_REV = 0x0960 | 48 | V | ||
–2 | 2 | % | ||||
VAC_REV = 0x0578 | 28 | V | ||||
–2 | 2 | % | ||||
VREV_ACC | VAC Voltage regulation accuracy in Reverse mode | VAC_REV = 0x02EE | 15 | V | ||
–2 | 2 | % | ||||
VAC_REV = 0x00FA | 5 | V | ||||
–2 | 2 | % | ||||
REVERSE MODE CURRENT REGULATION | ||||||
IIREV_ACC | Input current regulation accuracy in Reverse mode | RAC_SNS = 5mΩ, IAC_REV = 0x00A0 | 8 | A | ||
–3.5 | 3.5 | % | ||||
RAC_SNS = 5mΩ, IAC_REV = 0x0028 | 2 | A | ||||
–5.5 | 5.5 | % | ||||
MULTI-LEVEL CURRENT LIMIT (OVERLOAD MODE) | ||||||
ILIM2 | Temporary higher current limit for IIN or IOUT. Percentage above the IAC_REG or IOUT_REG register values. ILIM2 duration is tOVLD | EN_OVLD = 1 and OVLD_ILIM2 = 0 | 150 | % | ||
EN_OVLD = 1 and OVLD_ILIM2 = 1 | 200 | % | ||||
ILIM3 | Maximum temporary current limit for IIN or IOUT. ILIM3 duration is t3L_OVLD | Absolute maximum current limit across 5mΩ RAC_SNS and/or 5mΩ ROUT_SNS. EN_OVLD_3L = 1 and EN_OVLD = 1 | 20 | A | ||
ILIM2_IIN | Temporary higher current limit for IIN. Percentage above the IAC_REG register value | EN_OVLD = 1 and OVLD_ILIM2 = 0 | 150 | % | ||
EN_OVLD = 1 and OVLD_ILIM2 = 1 | 200 | % | ||||
ILIM2_IOUT | Temporary higher current limit for IOUT. Percentage above the IOUT_REG register value | EN_OVLD = 1 and OVLD_ILIM2 = 0 |
150 | % | ||
EN_OVLD = 1 and OVLD_ILIM2 = 1 |
200 | % | ||||
IBYPASS_OCP | Bypass mode over-current threshold | ROUT_SNS = 5mΩ, VSRP - VSRN rising, IOUT_REG = 5A | 4.5 | 5 | 5.5 | A |
THERMAL SHUTDOWN | ||||||
TSHUT | Thermal shutdown rising threshold | Temperature increasing | 150 | °C | ||
Thermal shutdown falling threshold | Temperature decreasing | 135 | °C | |||
REGN REGULATOR AND GATE DRIVE SUPPLY (DRV_SUP) | ||||||
VREGN | REGN LDO output voltage | IREGN = 20mA | 4.8 | 5 | 5.2 | V |
VAC = 5V, IREGN = 20mA | 4.35 | 4.6 | V | |||
IREGN | REGN LDO current limit | VREGN = 4.5V | 70 | mA | ||
VREGN_OK | REGN OK threshold to allow switching | REGN rising | 3.55 | V | ||
VDRV_UVPZ | DRV_SUP under-voltage threshold to allow switching | DRV_SUP rising | 3.7 | V | ||
VDRV_OVP | DRV_SUP over-voltage threshold to disable switching | DRV_SUP rising | 12.8 | 13.2 | 13.6 | V |
IAC_LOAD | VAC discharge load current | 16 | mA | |||
IBAT_LOAD | Battery (SRP) discharge load current | 16 | mA | |||
SWITCHING FREQUENCY AND SYNC | ||||||
fSW | Switching Frequency | RFSW_SYNC = 133kΩ | 212 | 250 | 288 | kHz |
RFSW_SYNC = 50kΩ | 425 | 500 | 575 | kHz | ||
VIH_SYNC | FSW_SYNC input high threshold | 1.3 | V | |||
VIL_SYNC | FSW_SYNC input low threshold | 0.4 | V | |||
PWSYNC | FSW_SYNC input pulse width | 80 | ns | |||
PWM DRIVERS | ||||||
RHIDRV1_ON | Buck side high-side turnon resistance | VBTST1 - VSW1 = 5V | 3.4 | Ω | ||
RHIDRV1_OFF | Buck side high-side turnoff resistance | VBTST1 - VSW1 = 5V | 1.0 | Ω | ||
VBTST1_REFRESH | Bootstrap refresh comparator threshold voltage | BTST1 falling, VBTST1 - VSW1 when low-side refresh pulse is requested | 2.7 | 3.1 | 3.9 | V |
RLODRV1_ON | Buck side low-side turnon resistance | VREGN = 5V | 3.4 | Ω | ||
RLODRV1_OFF | Buck side low-side turnoff resistance | VREGN = 5V | 1.0 | Ω | ||
tDT1 | Buck side dead time, both edges | 45 | ns | |||
RHIDRV2_ON | Boost side high-side turnon resistance | VBTST2 - VSW2 = 5V | 3.4 | Ω | ||
RHIDRV2_OFF | Boost side high-side turnoff resistance | VBTST2 - VSW2 = 5V | 1.0 | Ω | ||
VBTST2_REFRESH | Bootstrap refresh comparator threshold voltage | BTST2 falling, VBTST2 - VSW2 when low-side refresh pulse is requested | 2.7 | 3.1 | 3.9 | V |
RLODRV2_ON | Boost side low-side turnon resistance | VREGN = 5V | 3.4 | Ω | ||
RLODRV2_OFF | Boost side low-side turnoff resistance | VREGN = 5V | 1.0 | Ω | ||
tDT2 | Boost side dead time, both edges | 45 | ns | |||
ANALOG-TO-DIGITAL CONVERTER (ADC) | ||||||
tADC_CONV | Conversion-time, each measurement | ADC_SAMPLE[1:0] = 00 | 24 | ms | ||
ADC_SAMPLE[1:0] = 01 | 12 | ms | ||||
ADC_SAMPLE[1:0] = 10 | 6 | ms | ||||
ADCRES | Effective resolution | ADC_SAMPLE[1:0] = 00 | 14 | 15 | bits | |
ADC_SAMPLE[1:0] = 01 | 13 | 14 | bits | |||
ADC_SAMPLE[1:0] = 10 | 12 | 13 | bits | |||
ADC MEASUREMENT RANGE AND LSB | ||||||
IAC_ADC | Input current ADC reading (positive or negative) | Range with 5mΩ RAC_SNS | –20000 | 20000 | mA | |
LSB with 5mΩ RAC_SNS | 0.8 | mA | ||||
IOUT_ADC | Output current ADC reading (positive or negative) | Range with 5mΩ RBAT_SNS | –20000 | 20000 | mA | |
LSB with 5mΩ RBAT_SNS | 2 | mA | ||||
VAC_ADC | Input voltage ADC reading | Range | 0 | 65534 | mV | |
LSB | 2 | mV | ||||
VOUT_ADC | VO_SNS voltage ADC reading | Range | 0 | 65534 | mV | |
LSB | 2 | mV | ||||
TSADC | TS voltage ADC reading, as percentage of REGN | Range | 0 | 99.9 | % | |
LSB | 0.098 | % | ||||
I2C INTERFACE (SCL, SDA) | ||||||
VIH | Input high threshold level | 1.3 | V | |||
VIL | Input low threshold level | 0.4 | V | |||
VOL | Output low threshold level | Sink current = 5mA | 0.4 | V | ||
IIN_BIAS | High-level leakage current | Pull up rail 3.3V | 1 | µA | ||
LOGIC I/O PIN (CE, PG, STAT) | ||||||
VIH | Input high threshold level (CE) | 1.3 | V | |||
VOL | Output low threshold level (CE, PG, STAT) | Sink current = 5mA | 0.4 | V | ||
VIL | Input low threshold level (CE) | 0.4 | V | |||
IOUT_BIAS | High-level leakage current (CE, PG, STAT) | Pull up rail 3.3V | 1 | µA |