SLUSFB0 August 2024 BQ25758S
PRODUCTION DATA
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The DRV_SUP pin must maintain a valid voltage between DRV_UVP and DRV_OVP for proper operation of the switching power converter stage. This is true both in forward mode and in reverse mode.
When DRV_SUP pin voltage falls below DRV_UVP threshold, the switching converter stops operation, an INT pulse is asserted to signal the host, the DRV_OKZ_STAT, and DRV_OKZ_FLAG bits are set to signal the fault.
When DRV_SUP pin voltage rises above DRV_OVP threshold, the switching converter stops operation, an INT pulse is asserted to signal the host, the DRV_OKZ_STAT, and DRV_OKZ_FLAG bit are set to signal the fault.
When the DRV pin returns to normal operating range, the device automatically resumes switching in either forward or reverse mode as configured before the fault.