JAJSLW9B May   2020  – January 2023 BQ25798

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power-On-Reset
      2. 9.3.2  PROG Pin Configuration
      3. 9.3.3  Device Power Up from Battery without Input Source
      4. 9.3.4  Device Power Up from Input Source
        1. 9.3.4.1 Power Up REGN LDO
        2. 9.3.4.2 Poor Source Qualification
        3. 9.3.4.3 ILIM_HIZ Pin
        4. 9.3.4.4 Default VINDPM Setting
        5. 9.3.4.5 Input Source Type Detection
          1. 9.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 9.3.4.5.2 HVDCP Detection Procedure
          3. 9.3.4.5.3 Connector Fault Detection
      5. 9.3.5  Dual-Input Power Mux
        1. 9.3.5.1 ACDRV Turn On Condition
        2. 9.3.5.2 VBUS Input Only
        3. 9.3.5.3 One ACFET-RBFET
        4. 9.3.5.4 Two ACFETs-RBFETs
      6. 9.3.6  Buck-Boost Converter Operation
        1. 9.3.6.1 Force Input Current Limit Detection
        2. 9.3.6.2 Input Current Optimizer (ICO)
        3. 9.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 9.3.6.4 Pulse Frequency Modulation (PFM)
        5. 9.3.6.5 Device HIZ State
      7. 9.3.7  USB On-The-Go (OTG)
        1. 9.3.7.1 OTG Mode to Power External Devices
        2. 9.3.7.2 Backup Power Supply Mode
        3. 9.3.7.3 Backup Mode with Dual Input Mux
      8. 9.3.8  Power Path Management
        1. 9.3.8.1 Narrow VDC Architecture
        2. 9.3.8.2 Dynamic Power Management
      9. 9.3.9  Battery Charging Management
        1. 9.3.9.1 Autonomous Charging Cycle
        2. 9.3.9.2 Battery Charging Profile
        3. 9.3.9.3 Charging Termination
        4. 9.3.9.4 Charging Safety Timer
        5. 9.3.9.5 Thermistor Qualification
          1. 9.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 9.3.10 Integrated 16-Bit ADC for Monitoring
      11. 9.3.11 Status Outputs ( STAT, and INT)
        1. 9.3.11.1 Charging Status Indicator (STAT Pin)
        2. 9.3.11.2 Interrupt to Host ( INT)
      12. 9.3.12 Ship FET Control
        1. 9.3.12.1 Shutdown Mode
        2. 9.3.12.2 Ship Mode
        3. 9.3.12.3 System Power Reset
      13. 9.3.13 Protections
        1. 9.3.13.1 Voltage and Current Monitoring
          1. 9.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 9.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 9.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 9.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 9.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 9.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 9.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 9.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 9.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 9.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 9.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 9.3.14 Serial Interface
        1. 9.3.14.1 Data Validity
        2. 9.3.14.2 START and STOP Conditions
        3. 9.3.14.3 Byte Format
        4. 9.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.14.5 Target Address and Data Direction Bit
        6. 9.3.14.6 Single Write and Read
        7. 9.3.14.7 Multi-Write and Multi-Read
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
      2. 9.4.2 Register Bit Reset
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PV Panel Selection
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input (VBUS / PMID) Capacitor
        4. 10.2.2.4 Output (VSYS) Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 PROG Pin Configuration

At POR, the charger detects the PROG pin pull down resistance, then sets the charger default POR switching frequency and the battery cell count. Please follow the resistance list in Table 9-1 to set the desired POR switching frequency and battery cell count. The surface mount resistor with ±1% or ±2% tolerance is recommended.

Table 9-1 PROG Pin Resistance to Set Default Switching Frequency and Battery Cell Count
SWITCHING FREQUENCY CELL COUNT TYPICAL RESISTANCE AT PROG PIN
1.5 MHz 1s 3.0 kΩ
750 kHz 1s 4.7 kΩ
1.5 MHz 2s 6.04 kΩ
750 kHz 2s 8.2 kΩ
1.5 MHz 3s 10.5 kΩ
750 kHz 3s 13.7 kΩ
1.5 MHz 4s 17.4 kΩ
750 kHz 4s 27.0 kΩ

Some of the charging parameters default values are determined by the battery cell count identified by PROG pin configuration, which are summarized in the table below.

Table 9-2 Charging Parameters Dependent on Battery Cell Count
CELL (REG0x0A[7:6]) 1s 2s 3s 4s
ICHG (REG0x03/04) 1A 1 A 1 A 1 A
VSYSMIN (REG0x00[5:0]) 3.5 V 7 V 9 V 12 V
VREG (REG0x01/02) 4.2 V 8.4 V 12.6 V 16.8 V
VREG Range 3 V - 4.99 V 5 V - 9.99 V 10 V - 13.99 V 14 V - 18.8 V

After POR, the host can program the ICHG and VSYSMIN registers to any values within the ranges defined in the register tables. However, when programming the battery charging voltage (VREG), the host must ensure the VREG value is in the allowed range associated with the CELL register (REG0x0A[7:6]) setting defined in the table above. When the CELL register is changed, the ICHG, VSYSMIN and VREG registers are reset to the POR default values associated with the CELL setting.

For example, if the PROG pin resistance is a 2s battery configuration, the default POR CELL, ICHG, VSYSMIN and VREG settings will be 2s, 1 A, 7 V and 8.4 V respectively. After POR, the host can change ICHG and VSYSMIN to any values, and can change VREG to any value between 5V and 9.99V. Assuming that the CELL bits remain at the 2s battery configuration, then when the REG_RST bit is set or the watchdog timer expires, the registers are reset to default values with ICHG, VSYSMIN and VREG automatically returing to 1 A, 7V and 8.4V respectively.

When the CELL register is 2s battery configuration, any write out of the range of VREG (5 V - 9.99 V) is ignored by the charger. If VREG needs to be programmed out of the 5 V - 9.9 V range, such as 11 V, the CELL bits have to be changed to the 3s setting. Setting the CELL bits will also cause the ICHG, VSYSMIN and VREG registers to reset to their 3s POR default values of 1 A, 9 V and 12.6 V. Then the host can program VREG in the range of 10 V - 13.99 V. If, after changing the CELL bits to 3S, the REG_RST bit is set or the watchdog timer expires, the ICHG, VSYSMIN and VREG will then be reset to 1 A, 9 V and 12.6 V, regardless of the state of the PROG pin.