JAJSLW9B May   2020  – January 2023 BQ25798

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power-On-Reset
      2. 9.3.2  PROG Pin Configuration
      3. 9.3.3  Device Power Up from Battery without Input Source
      4. 9.3.4  Device Power Up from Input Source
        1. 9.3.4.1 Power Up REGN LDO
        2. 9.3.4.2 Poor Source Qualification
        3. 9.3.4.3 ILIM_HIZ Pin
        4. 9.3.4.4 Default VINDPM Setting
        5. 9.3.4.5 Input Source Type Detection
          1. 9.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 9.3.4.5.2 HVDCP Detection Procedure
          3. 9.3.4.5.3 Connector Fault Detection
      5. 9.3.5  Dual-Input Power Mux
        1. 9.3.5.1 ACDRV Turn On Condition
        2. 9.3.5.2 VBUS Input Only
        3. 9.3.5.3 One ACFET-RBFET
        4. 9.3.5.4 Two ACFETs-RBFETs
      6. 9.3.6  Buck-Boost Converter Operation
        1. 9.3.6.1 Force Input Current Limit Detection
        2. 9.3.6.2 Input Current Optimizer (ICO)
        3. 9.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 9.3.6.4 Pulse Frequency Modulation (PFM)
        5. 9.3.6.5 Device HIZ State
      7. 9.3.7  USB On-The-Go (OTG)
        1. 9.3.7.1 OTG Mode to Power External Devices
        2. 9.3.7.2 Backup Power Supply Mode
        3. 9.3.7.3 Backup Mode with Dual Input Mux
      8. 9.3.8  Power Path Management
        1. 9.3.8.1 Narrow VDC Architecture
        2. 9.3.8.2 Dynamic Power Management
      9. 9.3.9  Battery Charging Management
        1. 9.3.9.1 Autonomous Charging Cycle
        2. 9.3.9.2 Battery Charging Profile
        3. 9.3.9.3 Charging Termination
        4. 9.3.9.4 Charging Safety Timer
        5. 9.3.9.5 Thermistor Qualification
          1. 9.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 9.3.10 Integrated 16-Bit ADC for Monitoring
      11. 9.3.11 Status Outputs ( STAT, and INT)
        1. 9.3.11.1 Charging Status Indicator (STAT Pin)
        2. 9.3.11.2 Interrupt to Host ( INT)
      12. 9.3.12 Ship FET Control
        1. 9.3.12.1 Shutdown Mode
        2. 9.3.12.2 Ship Mode
        3. 9.3.12.3 System Power Reset
      13. 9.3.13 Protections
        1. 9.3.13.1 Voltage and Current Monitoring
          1. 9.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 9.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 9.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 9.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 9.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 9.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 9.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 9.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 9.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 9.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 9.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 9.3.14 Serial Interface
        1. 9.3.14.1 Data Validity
        2. 9.3.14.2 START and STOP Conditions
        3. 9.3.14.3 Byte Format
        4. 9.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.14.5 Target Address and Data Direction Bit
        6. 9.3.14.6 Single Write and Read
        7. 9.3.14.7 Multi-Write and Multi-Read
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
      2. 9.4.2 Register Bit Reset
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PV Panel Selection
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input (VBUS / PMID) Capacitor
        4. 10.2.2.4 Output (VSYS) Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 サード・パーティ製品に関する免責事項
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.5.4 Two ACFETs-RBFETs

In this scenario, both ACFET1-RBFET1 and ACFET2-RBFET2 are present. VAC1 / VAC2 is tied to the drain of ACFET1 / ACFET2, ACDRV1 / ACDRV2 is connected to the gate of ACFET1 / ACFET2. This structure is developed to support dual-input connected at VAC1 and VAC2. At POR, the charger detects both ACFET1-RBFET1 and ACFET2-RBFET2 present, then updates ACRB1_STAT and ACRB2_STAT to 1.

GUID-20201027-CA0I-SWLJ-LTJB-DPFPMCFFWKFB-low.gif Figure 9-4 Two ACFETs-RBFETs Structure Supporting One Input at VAC1 and One Input at VAC2
Table 9-7 Dual Input Configuration Summary
PIN OR REGISTER FIELD STATE
External MOSFETs ACFET1, RBFET1, ACFET2, RBFET2
VAC1 pin Connected to input source 1
VAC2 pin Connected to input source 2
ACDRV1 pin Connected to ACFET1/RBFET1 gate terminals
ACDRV2 pin Connected to ACFET2/RBFET2 gate terminals
ACRB1_STAT
0: ACFET1/RBFET1 Open (Path Disabled)
1: ACFET1/RBFET1 Closed (Path Enabled)
ACRB2_STAT
0: ACFET2/RBFET2 Open (Path Disabled)
1: ACFET2/RBFET2 Closed (Path Enabled)
DIS_ACDRV
0: Allow ACDRV1 or ACDRV2 on if all requirements met
1: Force ACDRV1 and ACDRV2 off
EN_ACDRV1
0: Force ACDRV1 Off
1: Turn ACDRV1 On if all requirements met
EN_ACDRV2
0: Force ACDRV2 Off
1: Turn ACDRV2 On if all requirements met

In dual input mode, the ACDRV automatically turns on the ACFET-RBFET of the path where a valid input is first presented, without host intervention.If the two inputs are presented at VAC1 and VAC2 exactly at the same time, ACFET1-RBFET1 with higher priority (port #1 is primary) is turned on while ACFET2-RBFET2 stays off (port #2 is secondary). EN_ACDRV1 is automatically set to 1. If a valid input is presented on the second path while the first path is already on with a valid input, the ACFET-RBFET of the second path remains off. If desired, the host may manually perform a switch between power paths by switching the values of EN_ACDRV1 and EN_ACDRV2. Both EN_ACDRV bits may be updated in a single I2C write operation to minimize the transition time. Note that programming EN_ACDRV1 = 1, EN_ACDRV2 = 1 at the same time to turn on both ACFET1-RBFET1 and ACFET2-RBFET2 is not allowed, and will be ignored by the charger.

To transition from one input to the other, the device first turns off the initially active ACFET-RBFET pair, waits until the VBUS voltage drops lower than VBUS_PRESENT, and then enables the new ACFET-RBFET pair. During this change over, the converter stops switching for a short period of time.

If two valid voltages are present at VAC1 and VAC2 and the source on the connected path becomes invalid because of VAC_UVLO, VAC_OV or IBUS_OC, the charger automatically swaps the input without any host engagement. Any time that the converter autonomously swaps the source paths, it will also update the EN_ACDRV1 and EN_ACDRV2 bits accordingly in order to indicate the active power path.

With only one valid input presented at either VAC1 or VAC2, the ACFET1-RBFET1 and ACFET2-RBFET2 can not be both turned off by setting REG0x13[7:6] = 00. Instead, the host should set DIS_ACDRV = 1 to force both ACFET-RBFET pairs off. With input sources present at both VAC1 and VAC2, the host can turn off the two ACFET-RBFET pairs by setting either REG0x13[7:6] = 00 or DIS_ACDRV = 1.