JAJSCJ2 データシート

JAJSCJ2 October 2016

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

YFF|42
- MXBG341

サーマルパッド・メカニカル・データ

発注情報

jajscj2_oa

8 Detailed Description

8.1 Overview

The bq25872 is an I²C controlled device and a single cell Li-Ion battery charger. The device allows 7-A charging current with 13-mΩ MOSFETs for minimum power loss. A 10 -bit ADC, four linear regulation loops and multiple OVP and OCP are integrated for host monitoring and safe operation of the device.

8.1.1 Device Protection Overview

The following table summarizes the protection features implemented in the device.

Table 1. Protection Features Overview

PROTECTION NAME	DESCRIPTION	RESPOND
VUSB OVP	Monitors VUSB voltage and compares to the voltage defined by OVPSET and VUSBOVP_I2C (REG29[3:2])	Turn off external OVPFET via OVPGATE
VBUS_OVP	Monitors VBUS voltage and compares to the threshold programmed in REG 0A	Turn off load switch after a deglitch time of t_{VBUS_OVP}
VOUT_REG	Monitors VOUT voltage and compares to the threshold programmed in REG 0B	Enable linear regulation of battery switch within a response time of t_{LDO_RES}
VOUT_OVP	Monitors VOUT voltage and compares to 1.04 times of the threshold programmed in REG 0B	Turn off load switch after a deglitch time of t_{VOUT_OVP}
VDROP_OVP	Monitors voltage difference between VBUS and VOUT (VBUS – VOUT) and compares to the threshold programmed in REG 0C	Turn off load switch after a deglitch time of t_{VDROP_OVP}
VDROP_ALM	Monitors voltage difference between VBUS and VOUT (VBUS – VOUT) and compares to the threshold programmed in REG 0D	INT is asserted low to alert host
VBAT_REG	Monitors VBAT voltage and compares to the threshold programmed in REG 0E	Enable linear regulation of battery switch within a response time of t_{LDO_RES}
VBAT_OVP	Monitors VBAT voltage and compares to 1.04 times of the threshold programmed in REG 0E	Turn off load switch after a deglitch time of t_{VBAT_OVP}
IBAT_REG	Monitors battery current measured by sensing resistor and compares to the threshold programmed in REG 0F	Enable linear regulation of battery switch within a response time of t_{LDO_RES}
IBAT_OCP	Monitors VBAT voltage and compares to 1.05 times of the threshold programmed in REG 0E	Turn off load switch after a deglitch time of t_{VBAT_OVP}
IBUS_OCP	Monitors input current and compares to the threshold programmed in REG 09	Turn off load switch after a deglitch time of t_{IBUS_OCP}
IBUS_REG	Monitors input current and compares to the threshold programmed in REG 10	Enable linear regulation of battery switch within a response time of t_{LDO_RES}
IBUS_RCP	Monitors current flowing from battery to adaptor and compares to the threshold selected in REG 06	Turn off load switch after a deglitch time of t_{IBUS_RCP}
TS_BUS_OTP	Monitors temperature based on voltage measured by a negative temperature coefficient (NTC) resistor at VBUS and compares to the threshold programmed in REG 11	Turn off load switch after a deglitch time of t_{TS_OTP}
TS_BAT_OTP	Monitors temperature based on voltage measured by a negative temperature coefficient (NTC) resistor at battery and compares to the threshold programmed in REG 12	Turn off load switch after a deglitch time of t_{TS_OTP}

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Device Power Up

The internal bias circuits of the device are powered from higher of the two voltages among VUSB, VBUS and VOUT as long as one of the pins is above its respective PRESENT threshold (VUSB_PRESENT, VBUS_PRESENT, or VOUT_PRESENT). Once either V_VUSB > VUSB_PRESENT,V_VBUS > VBUS_PRESENT, or V_VOUT > VOUT_PRESENT is qualified, the device is considered to have a valid power supply. However, the device will begin to draw current from VBUS or VOUT (depending upon which supply is present) once either supply is above its respective UVLO threshold.

8.3.2 Battery Switch (Q1 + Q2)

The device contains an integrated 13mΩ battery switch that is capable of handling up to 7 A of current. This battery switch can be controlled by the host via CHG_EN I²C bit. The device can be disabled, including the battery switch and the I²C core, by pulling the EN pin low. To turn on the battery switch charger for conduction, the EN pin must be pulled high, CHG_EN bit must be set to ‘1’, and no fault conditions must be present (unless they have been disabled in EVENT_1_EN register). See EVENT_1 and EVENT_2 registers for a list of faults/events. In the event of a fault/event, the battery switch will be automatically disabled, and the host will be notified via the INT for error reporting if the corresponding event bit is unmasked in the EVENT_x_MASK registers.

In order to ensure that the IBUS OCP threshold is not falsely tripped during turn-on of the battery switch, the device employs a soft-start scheme where the battery switch is slowly turned to minimize the inrush current. The rise time of VOUT is t_{ON_VOUT}.

8.3.3 Integrated 10-bit ADC for Monitoring

With the integrated 10-bit ADC of the device, the user application can monitor the voltage of VUSB, the voltage and current of VBUS, voltage of VOUT and VUSB, and the voltage and current of the battery. The ADC is also used for temperature reporting of the internal junction temperature, battery temperature (via external resistor divider and NTC thermistor), and VBUS connector temperature (via external resistor divider and NTC thermistor). The integrated ADC has a conversion time of t_{ADC_CONV} for each parameter (except IBAT_ADC which has conversion time of 2 x t_{ADC_CONV} ). The total conversion time of all parameters (in 1-shot mode) is between 80 µs and 140 µs. The rate at which the ADC output registers are updated depends on the settings of ADC_AVG_EN, ADC_SAMPLES, and the parameter conversions that have been enabled in the ADC_MASK register.

To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either V_VUSB> VUSB_PRESENT, V_VBUS> VBUS_PRESENT or V_VOUT > VOUT_PRESENT is valid. If ADC_EN is set to ‘1’ before VUSB or VBUS or VOUT reach their respective PRESENT threshold, then ADC conversion will be postponed until one of the power supplies reaches their respective PRESENT threshold. If EN pin is asserted low, then ADC conversion is not allowed.

The integrated ADC has two conversion rate options – 1-shot conversion (only one conversion) and continuous conversion (back-to-back conversions). To select the appropriate conversion rate, the ADC_RATE bit must be set accordingly (‘0’ for 1-shot, ‘1’ for continuous). If ADC_AVG_EN is set to ‘0’, the ADC will convert instantaneous measurements. If ADC_AVG_EN is set to ‘1’, the average measurement of a parameter (in both continuous and 1-shot mode) will be determined by the setting of ADC_SAMPLES. If the user reads the output registers before the ADC averaging is complete, then the read-back value would be unchanged from the previous converted measurement. However, the value in the register will not change during the read-back of the register(s). If the measured signal is outside of the range of the ADC output register in question, the reported value in the ADC will be clamped to the min/max of the range specified. When ADC_EN is changed from 1 to 0, the ADC registers will maintain their values from the previous converted measurement.

The user application has the option of selecting which parameters (voltage, current, temperature) the ADC needs to convert when the ADC is set to continuous conversion mode (ADC_RATE is set to ‘1’) or in 1-shot mode (ADC_RATE is set to ‘0’). By default, all parameters (VUSB_ADC, IBUS_ADC, VBUS_ADC, IBAT_ADC, VBAT_ADC, VOUT_ADC, VDROP_ADC, TBUS_ADC, TBAT_ADC, TDIE_ADC) will be converted in 1-shot and continuous conversion mode unless disabled in the ADC_MASK register. If an ADC parameter is masked (by setting the corresponding bit in the ADC_MASK_x register), then the value in that register will be from the last valid ADC conversion or the default POR value (which is all zeros if no conversions have taken place). If an ADC parameter is masked in the middle of an ADC measurement cycle, the device will finish the conversion of that parameter in the current conversion cycle and will not convert that parameter starting the next conversion cycle. Even though no conversion takes place when all ADC measurement parameters are masked off, the ADC circuitry is active and ready to begin conversion as soon as one of the bits in the ADC_MASK register is set to ‘0’.

The ADC_DONE bit signals when a 1-shot mode conversion is completed. During continuous conversion mode, this bit is always set to ‘0’.

The ADC_EN bit controls when the ADC is enabled for a conversion. Upon enabling the ADC, the ADC conversion will follow the settings in ADC_AVG_EN, ADC_SAMPLE, and ADC_RATE.

ADC conversion operates independently of the faults present in the device. ADC conversion will continue even after a fault has occurred (that causes the battery switch to be disabled), and the host must set ADC_EN = ‘0’ to disable ADC.

ADC readings are only valid for DC states of the signals, not for transients.

8.3.4 Linear Regulation Mode (LDO)

The device employs LDO mode that helps regulate VOUT voltage, battery voltage, input current and battery current. In an event that the VOUT_REG, VBAT_REG, IBUS_REG or IBAT_REG threshold is exceeded, the battery switch will act as an LDO and will regulate VOUT, VBAT, IBUS and IBAT (depending upon which threshold is exceeded). The purpose of LDO mode is to provide temporary protection until the host is able to read the EVENT_x registers (upon INT trigger), ADC output registers, and then update the adapter voltage accordingly.

When VOUT_REG, VBAT_REG, or IBAT_REG threshold is exceeded, the response time of the LDO will be 1ms. Depending upon which LDO mode event occurs, the corresponding bit (VBAT_REG_LDO, IBAT_REG_LDO, VOUT_REG_LDO) will be set in EVENT_1 register and INT will be asserted low to alert the host (if the corresponding bit is not masked in EVENT_1_MASK register).

8.3.5 Protection Features

The device contains various protection features that are active depending upon the states of various inputs:

If V_VUSB > VUSB_PRESENT, V_VBUS > VBUS_PRESENT, V_VOUT > VOUT_PRESENT, EN asserted high, and CHG_EN = ‘1’
- Active protection: VBUS_OVP, IBUS_OCP, VOUT_OVP, VBAT_OVP, IBAT_OCP, SCP, RCP, VDROP_OVP
If V_VUSB > VUSB_PRESENT, V_VBUS > VBUS_PRESENT, V_VOUT > VOUT_PRESENT, EN asserted high, and CHG_EN = ‘0’
- Active protection: VBUS_OVP, IBUS_OCP, VOUT_OVP, IBAT_OCP, SCP, RCP, VDROP_OVP
- VBAT_OVP active until VBAT OVP condition is over (protection becomes inactive on falling threshold of VBAT_OVP, which is 102% of VBAT_REG setting)
If V_VUSB > VUSB_PRESENT, EN asserted low, and CHG_EN = ‘0’
- Active protection: VUSB_OVP
If V_VUSB < VUSB_PRESENT, V_VBUS > VBUS_PRESENT, V_VOUT > VOUT_PRESENT, and CHG_EN = ‘0’
- Active protection: VUSB_OVP
- VOUT_PRESENT, VBUS_PRESENT, and VUSB_PRESENT comparators active

Tripping any of these protection faults will cause the battery switch to be disabled (unless the protection is disabled in EVENT_1_EN and EVENT_2_EN registers) and an interrupt to be issued on the INT pin (see INT Pin, EVENT_x Registers, EVENT_x_MASK Registers section for details of when INT is toggled).

8.3.5.1 Reverse Current Protection (RCP)

The device monitors the current flow from VBUS to VOUT to ensure there is no reverse current (current flow from VOUT to VBUS). In an event that a reverse current flow is detected, the battery switch is disabled within t_{OFF_FET} after a deglitch time of t_IREV and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’ to enable the power switch again. The RCP threshold is set by the RCP_SET bit.

Reverse current protection is always active when the device has valid power. The RCP threshold is based on the RCP_SET bit setting in the CONTROL register. It has a response delay of t_IREV. When RCP is tripped, IBUS_IREV_FLT bit in the EVENT_1 register is set to ‘1’, and INT is asserted low to alert the host (unless masked by IBUS_IREV_MASK).

8.3.5.2 Internal Thermal Shutdown

The device monitors the die junction temperature and the battery switch is disabled when device junction temperature reaches TSHUT within t_{OFF_FET} and CHG_EN is set to ‘0’ . When the internal thermal shutdown is triggered, INT is asserted low to alert the host, and the device temperature must drop by TSHUT_HYS before the battery switch can be enabled again (host must enable battery switch). While the TSHUT condition persists (and before the junction temperature dropped by TSHUT_HYS), all other functions are unaffected.

If the DIE_TEMP_FLT threshold has been crossed, TSHUT_FLT bit in EVENT_2 register is set to ‘1’, and INT will assert low to alert the host (no mask bit for TSHUT_FLT). After the TSHUT_FLT is cleared by the host with a register read, it is possible the TSHUT_FLT bit is set again if the die junction temperature has not reduced by TSHUT_HYS.

DIE_TEMP_FLT allows the user to select TSHUT thresholds between different junction temperatures as the thermal shutdown point. DIE_TEMP_ADC is the die (junction) temperature of the device that is measured via the 10-bit ADC.

The ADC measurement (DIE_TEMP_ADC) is independent of the TSHUT fault that triggers TSHUT_FLT in the EVENT_x register. Therefore, it is possible to have the ADC output value be a higher value that the DIE_TEMP_FLT threshold, while the TSHUT fault has not yet been triggered.

8.3.5.3 Input Overvoltage Protection

The device integrates the functionality of an overvoltage protector. The device can be paired with an external N-channel FET to block input voltages higher than the setting programmed by OVPSET pin. The device senses the input (via VUSB) and turns the external N-channel FET on or off (via OVPGATE pin) to protect the downstream system. This eliminates the need for a separate OVP chip to protect the overall system. The integrated OVP feature has a reaction time of t_{OFF_FLT} (the actual time to turn off OVP FET will be longer and depends upon the FET gate capacitance) and does not depend on the EN pin status (i.e., feature is always active as long as V_VUSB > VUSB_PRESENT). If the EN pin is pulled high, then I²C communication to the device is available, and the OVP threshold can then be changed via the VUSBOVP_I2C bits. The final VUSB OVP threshold is set by the lower setting of the OVPSET pin and the VUSBOVP_I2C bits. VUSBOVP_I2C bits are not reset when EN is asserted low and are only reset by REG_RST or a POR event.

8.3.5.3.1 OVPSET pin

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

The default power up OVP threshold can be set via the OVPSET pin with a single external resistor to one of three preset thresholds – 6.5 V, 10.5 V, and 14 V. The OVPSET pin will source a current to determine the resistance on the pin, and then set the OVP threshold accordingly. The OVPSET pin will follow these threshold assignments:

Highest pin threshold (floating) = 6.5-V OVP threshold
Lowest pin threshold (tied to GND) = 14.5-V OVP threshold
Mid-point pin threshold (22 kΩ to GND) = 10.5 V

8.3.5.4 IBUS and VBUS Protection

Over-current protection on VBUS (IBUS_OCP) monitors the current flow from VBUS to VOUT pins. IBUS_OCP protection is always active when the battery switch is enabled, and the protection has a deglitch time that depends on the OCP_RES setting as described below.

If OCP_RES = ‘0’ (blanking mode), the device will wait t_{IBUS_OCP_BLANK} before disabling the battery switch within t_{OFF_FET} and setting CHG_EN to ‘0’. When the battery switch is disabled, IBUS_OCP_FLT is set to ‘1’. If during the t_{IBUS_OCP_BLANK} duration a short circuit protection scenario occurs, then the device will follow the behavior as listed in short circuit protection (SCP). Once the battery switch is disabled, CHG_EN is set to ‘0’ and host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again.

Figure 11. IBUS OCP and SCP

If OCP_RES = ‘1’ (hiccup mode), the device will turn off the battery switch within t_{IBUS_OCP} and will attempt to turn on the battery switch every t_{IBUS_OCP_HP}, up to seven times before latching off the battery switch. Upon latching off after the seventh try, IBUS_OCP_FLT is set to ‘1’. Once the battery switch is latched off, CHG_EN is set to ‘0’ and host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again.

Figure 12. IBUS OCP in Hiccup Mode

VBUS over-voltage protection (VBUS_OVP) monitors the voltage on VBUS. VBUS_OVP protection is always active when the device voltage is above at least one PRESENT level (VBUS or VOUT), and the protection has a selectable deglitch time set by VBUS_OVP_DLY. When VBUS_OVP threshold is reached, the battery switch is turned off in t_{VBUS_OVP} and latched off. If the VBUS_OVP or IBUS_OCP value written to the register is greater than the max defined value for the register, then the corresponding register will be set to the highest defined value.

If a threshold has been crossed (IBUS_OCP or VBUS_OVP), the appropriate bit in the EVENT_1 register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_1_MASK bit is not set to ‘1’ for the corresponding bit in the EVENT_1 register, then INT will assert low to alert the host of a fault.

8.3.5.5 IBAT and VBAT Protection

The device monitors current through the battery by monitoring the voltage across the external, series battery sense resistor. The differential voltage of this sense resistor is measured on SRP and SRN. A 10-mΩ series resistor is recommended for battery current monitoring. A lower resistor value can be used, but it will result in lower measurement accuracy. A higher resistor value can be used, but it will result in decreased charging efficiency.

When the IBAT_REG threshold is reached, the device will go into LDO mode to regulate the battery current at the IBAT_REG threshold. See LDO mode section for more details about the device operation during LDO mode. If the IBAT_OCP threshold is reached and IBAT_OCP protection has been enabled, the battery switch will be disabled within t_{OFF_FET} after a deglitch time of t_{IBAT_OCP} and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again.

The device monitors battery voltage by measuring the differential voltage on BATP and BATN pins. When the VBAT_REG threshold is reached, the device will go into LDO mode to regulate the battery voltage at the VBAT_REG threshold. See LDO mode section for more details about the device operation during LDO mode. If the VBAT_OVP threshold is reached and VBAT_OVP protection is enabled, the battery switch will be disabled within t_{OFF_FET} after a deglitch time of t_{VBAT_OVP} and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again. If the VBAT_REG or IBAT_REG value written to the register is greater than the max defined value for the register, then the corresponding register will be set to the highest defined value.

If a threshold has been reached (IBAT_REG, VBAT_REG, IBAT_OCP or VBAT_OVP), the appropriate bit in the EVENT_x register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is not set to ‘1’ for the corresponding bit in the EVENT_x register, then INT will assert low to alert the host of a fault.

8.3.5.6 VOUT Protection

The device monitors voltage on VOUT when the device has a valid power supply. When the VOUT_REG threshold is reached, the device will go into LDO mode to regulate the VOUT voltage at the VOUT_REG threshold. See LDO mode section for more details about the device operation during LDO mode. If the VOUT_OVP threshold is reached and VOUT_OVP protection is enabled, the battery switch will be disabled within t_{OFF_FET} after a deglitch time of t_{VOUT_OVP} and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again. If the VOUT_REG value written to the register is greater than the max defined value for the register, then VOUT_REG will be set to the highest defined value for the register.

If a threshold has been reached (VOUT_REG or VOUT_OVP), the appropriate bit in the EVENT_1 register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is not set to ‘1’ for the corresponding bit in the EVENT_x register, then INT will assert low to alert the host of a fault.

8.3.5.7 VDROP Protection

VDROP is the voltage difference from VBUS to VOUT and can be used to monitor the health of MOSFET and power loss of the device. There are two VDROP thresholds, VDROP alarm (VDROP_ALM) and VDROP fault (VDROP_FLT). VDROP_ALM is an indicator (via I²C register bit and INT) to alert the host that the voltage differential between VBUS and VOUT is higher than normal, and that the host to should take action to reduce this drop. VDROP_OVP is a fault threshold that results in the battery switch being disabled within t_{OFF_FET} after a deglitch time of t_{VDROP_OVP} and CHG_EN set to ‘0’ when VDROP_OVP protection is enabled. Host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again. If the VDROP_OVP or VDROP_ALM value written to the register is greater than the max defined value for the register, then the corresponding register will be set to the highest defined value.

If a threshold has been reached (VDROP_ALM or VDROP_OVP), the appropriate bit in the EVENT_1 register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is not set to ‘1’ for the corresponding bit in the EVENT_x register, then INT will assert low to alert the host of a fault.

VDROP_ALM does not affect the state of the battery switch and only causes INT to assert low when the threshold is crossed. VDROP_OVP does turn off the battery switch and causes INT to assert low if this threshold is crossed. Therefore, if VDROP_ALM threshold is set higher than the VDROP_OVP threshold accidentally (user error), then VDROP_ALM functionality is never triggered since VDROP_OVP threshold will turn off the battery switch and assert INT low.

NOTE

The threshold of VDROP_OVP and VDROP_ALM is around 13 mV lower than the actual setting when VDROP ADC is enabled.

8.3.5.8 VBUS Temperature (TS_BUS_FLT) and Battery Temperature (TS_BAT_FLT)

TBUS_OTP and TBAT_OTP protection is active whenever the device has a valid power supply. The purpose of VBUS temperature is to have connector temperature monitor to improve user experience. TS_BUS and TS_BAT both rely on a resistor divider that has an external pull-up voltage. Internally, the TS_BUS and TS_BAT pins are clamped to 2.42 V. Place a negative coefficient thermistor in parallel to the low-side resistor. A fault on the TS_BUS and TS_BAT pin is triggered on the falling edge of the voltage threshold (signifying a “hot” temperature).

If the TBUS_OTP or TBAT_OTP threshold is reached, the battery switch will be disabled within t_{OFF_FET} after a deglitch time of t_{TS_OTP} and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again. If the TS_BUS_FLT or TS_BAT_FLT value written to the register is greater than the max defined value for the register, then the corresponding register will be set to the highest defined value.

For TS_BUS_FLT and TS_BAT_FLT, if a threshold has been crossed, the appropriate bit in the EVENT_x register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is not set to ‘1’ for the corresponding bit in the EVENT_1 register, then INT will toggle to alert the host of a fault.

NOTE

TS_BUS_FLT will not trip when TS_BUS ADC is enabled.

8.3.6 I²C Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I²C communication to the device is available as long as V_VUSB> VUSB_UVLO or V_VBUS > VBUS_UVLOor V_VOUT > VOUT_UVLO. I2C™ is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required, a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address set by the ADDR pin. The device receives control inputs from the master device like micro controller or a digital signal processor through REG00-REG29 and REG40. Register read between REG29 and REG39 beyond REG40 returns 0xFF. The I²C interface supports standard mode (up to 100 kbit/s), fast mode (up to 400 kbit/s), and fast mode plus (up to 1 Mbit/s). Connect the SDA and SCL pins to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are high. The SDA and SCL pins are open drain.

The device supports 7-bit addressing. The 8th bit will change depending upon the command (read or write) that is issued. The device’s 7-bit address is defined as shown in the image below.

Figure 13. Slave Address

8.3.6.1 Data Validity

Figure 14. Bit Transfer on the I²C Bus

8.3.6.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

Figure 15. START and STOP Conditions

8.3.6.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Figure 16. Data Transfer on the I²C Bus

8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.6.5 Slave Address and Data Direction bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

Figure 17. Complete Data Transfer

Figure 18. Single Read

If the register address is not defined, the charger device send back NACK and go back to the idle state.

8.3.6.6 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG08.

Figure 19. Multi-Read

EVENT_1, EVENT_2, and EVENT_3 keep all the information from last read until the host issues a new read. For example, if VBUS_OVP fault occurs but recovers later, the fault register EVENT_1 reports the fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault information at present, the host has to read EVENT_1, EVENT_2, and EVENT_3 for the second time.

8.4 Device Functional Modes

The device is a host controlled device. After power-on-reset, all the registers are in the default settings. All the device parameters can be programmed by the host. Writing 1 to REG 06 [0] will reset all registers to default setting. When watchdog timer expires, charge enable bit (REG06 [4]) and ADC enable bit (REG07 [3]) will be reset to default settings. To prevent watchdog timer expiring, the host has to read or write any register before the watchdog timer expires, or disable watchdog timer by setting REG06 [3:2] = 00.

Figure 20. Operation Mode

8.5 I²C Register Maps

8.5.1 I²C Register Summary Table

Table 2. I²C Register Summary Table

I²C ADDRESS	R/W	REGISTER NAME	DESCRIPTION	POR STATE
0x00	R	DEVICE_INFO	Device rev and device ID	0x03
0x01	R/W	EVENT_1_MASK	Masks INT toggle of events in EVENT_1	0x00
0x02	R/W	EVENT_2_MASK	Masks INT toggle of events in EVENT_2	0x00
0x03	R	EVENT_1	First event register	0x00
0x04	R	EVENT_2	Second event register	0x00
0x05	R/W	EVENT_1_EN	Enables/disables protection in EVENT_1 register	0xFE
0x06	R/W	CONTROL	Settings for battery switch, watchdog, reset, and RCP threshold	0x2C
0x07	R/W	ADC_CTRL	Contains ADC control bits such as enable/disable, rate, and number of samples to take	0x87
0x08	R/W	ADC_MASK	Controls which parameters the ADC converts – first set	0xFF
0x09	R/W	PROTECTION	Deglitch setting and VBUS OCP threshold	0xA0
0x0A	R/W	VBUS_OVP	Sets VBUS OVP threshold	5.49 V
0x0B	R/W	VOUT_REG	Sets VOUT voltage regulation threshold	4.4 V
0x0C	R/W	VDROP_OVP	Sets the VDROP OVP threshold	300 mV
0x0D	R/W	VDROP_ALM	Sets the VDROP alarm threshold	100 mV
0x0E	R/W	VBAT_REG	Battery (BATP – BATN) regulation threshold	4.3 V
0x0F	R/W	IBAT_REG	Sets battery current regulation threshold	2 A
0x10	R/W	IBUS_REG	Sets VBUS REG threshold	5 A
0x11	R/W	TS_BUS_FLT	Sets VBUS temperature threshold	0.6 V
0x12	R/W	TS_BAT_FLT	Sets battery temperature threshold	0.7 V
0x13	R	VBUS_ADC	ADC output of VBUS voltage measurement	0x00
0x14	R	VBUS_ADC	ADC output of VBUS voltage measurement	0x00
0x15	R	IBUS_ADC	ADC output of VBUS current measurement	0x00
0x16	R	IBUS_ADC	ADC output of VBUS current measurement	0x00
0x17	R	VOUT_ADC	ADC output of VOUT voltage measurement	0x00
0x18	R	VOUT_ADC	ADC output of VOUT voltage measurement	0x00
0x19	R	VDROP_ADC	ADC output of (VBUS – VOUT) voltage measurement	0x00
0x1A	R	VDROP_ADC	ADC output of (VBUS – VOUT) voltage measurement	0x00
0x1B	R	VBAT_ADC	ADC output of battery voltage measurement	0x00
0x1C	R	VBAT_ADC	ADC output of battery voltage measurement	0x00
0x1D	R	IBAT_ADC	ADC output of battery current measurement	0x00
0x1E	R	IBAT_ADC	ADC output of battery current measurement	0x00
0x1F	R	TBUS_ADC	ADC output of TS_BUS voltage	0x00
0x20	R	TBUS_ADC	ADC output of TS_BUS voltage	0x00
0x21	R	TBAT_ADC	ADC output of TS_BAT voltage	0x00
0x22	R	TBAT_ADC	ADC output of TS_BAT voltage	0x00
0x23	R	DIE_TEMP_ADC	ADC output of the die temperature	0x00
0x24	R/W	EVENT_3_EN	Enables/disables protection in EVENT_3 register	0x04
0x25	R/W	EVENT_3_MASK	Masks INT toggle of events in EVENT_3	0x00
0x26	R/W	EVNET_3	Third event register	0x00
0x27	R	VUSB_ADC	ADC output of VUSB voltage	0x00
0x28	R			0x00
0x29	R/W	CONTROL_2	VUSB settings	0x6E
0x40	R/W	TDIE_TEMP_FLT	Setting die over temperature fault threshold	0x03