JAJSFD8A September 2016 – May 2018 BQ25890H
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description | |
---|---|---|---|---|---|
7 | DP_DAC[2] | R/W | by REG_RST | D+ Pin Output Driver
000 – HiZ mode (Default) 001 – 0V (V0P0_VSRC ) 010 – 0.6V (V0P6_VSRC ) 011 – 1.2V (V1P2_VSRC ) 100 – 2.0V (V2P0_VSRC ) 101 – 2.7V (V2P7_VSRC ) 110 – 3.3V (V3P3_VSRC ) 111 – Reserved Register bits are reset to default value when input source is plugged-in and can be changed after D+/D- detection is completed. |
|
6 | DP_DAC[1] | R/W | by REG_RST | ||
5 | DP_DAC[0] | R/W | by REG_RST | ||
4 | DM_DAC[2] | R/W | by REG_RST | D- Pin Output Driver
000 – HiZ mode (Default) 001 – 0V (V0P0_VSRC ) 010 – 0.6V (V0P6_VSRC ) 011 – 1.2V (V1P2_VSRC ) 100 – 2.0V (V2P0_VSRC ) 101 – 2.7V (V2P7_VSRC ) 110 – 3.3V (V3P3_VSRC ) 111 – Reserved Register bits are reset to default value when input source is plugged-in and can be changed after D+/D- detection is completed. |
|
3 | DM_DAC[1] | R/W | by REG_RST | ||
2 | DM_DAC[0] | R/W | by REG_RST | ||
1 | EN_12V | R/W | by REG_RST | Enable 12V detection for MaxCharge and HVDCP
0 – Disable 12V Detection (default) 1 – Enable 12V Detection |
|
0 | VINDPM_OS | R/W | by REG_RST | Input Voltage Limit Offset
0 – 400mV 1 – 600mV (default) |