JAJSFD7C July 2015 – May 2018
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VBUS/BAT POWER UP | |||||||
tBADSRC | Bad Adapter detection duration | 30 | msec | ||||
BAT OVER-VOLTAGE PROTECTION | |||||||
tBATOVP | Battery over-voltage deglitch time to disable charge | 1 | µs | ||||
BATTERY CHARGER | |||||||
tRECHG | Recharge deglitch time | 20 | ms | ||||
CURRENT PULSE CONTROL | |||||||
tPUMPX_STOP | Current pulse control stop pulse | 430 | 570 | ms | |||
tPUMPX_ON1 | Current pulse control long on pulse | 240 | 360 | ms | |||
tPUMPX_ON2 | Current pulse control short on pulse | 70 | 130 | ms | |||
tPUMPX_OFF | Current pulse control off pulse | 70 | 130 | ms | |||
tPUMPX_DLY | Current pulse control stop start delay | 80 | 225 | ms | |||
BATTERY MONITOR | |||||||
tCONV | Conversion time | CONV_RATE(REG02[6]) = 0 | 8 | 1000 | ms | ||
QON AND SHIPMODE TIMING | |||||||
tSHIPMODE | QON low time to turn on BATFET and exit ship mode | TJ = –10°C to +60°C | 0.9 | 1.3 | s | ||
tQON_RST | QON low time to enable full system reset | TJ = –10°C to +60°C | 16 | 23 | s | ||
tBATFET_RST | BATFET off time during full system reset | TJ = –10°C to +60°C | 250 | 400 | ms | ||
tSM_DLY | Enter ship mode delay | TJ = –10°C to +60°C | 10 | 15 | s | ||
I2C INTERFACE | |||||||
fSCL | SCL clock frequency | 400 | kHz | ||||
DIGITAL CLOCK and WATCHDOG TIMER | |||||||
fLPDIG | Digital low power clock | REGN LDO disabled | 18 | 30 | 45 | kHz | |
fDIG | Digital clock | REGN LDO enabled | 1320 | 1500 | 1680 | kHz | |
tWDT | Watchdog reset time | WATCHDOG (REG07[5:4])=11, REGN LDO disabled | 100 | 160 | s | ||
WATCHDOG (REG07[5:4])=11, REGN LDO enabled | 136 | 160 | s |