SLUSCH6B March   2016  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 PSEL Pin Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Power Path Management
        1. 8.2.4.1 Dynamic Power Management
      5. 8.2.5  Battery Charging Management
        1. 8.2.5.1 Autonomous Charging Cycle
        2. 8.2.5.2 Battery Charging Profile
        3. 8.2.5.3 Charging Termination
        4. 8.2.5.4 Charging Safety Timer
      6. 8.2.6  Battery Monitor
      7. 8.2.7  Status Outputs (PG, STAT, and INT)
        1. 8.2.7.1 Power Good Indicator (PG)
        2. 8.2.7.2 Charging Status Indicator (STAT)
        3. 8.2.7.3 Interrupt to Host (INT)
      8. 8.2.8  Thermal Regulation and Thermal Shutdown
        1. 8.2.8.1 Thermal Protection in Buck Mode
      9. 8.2.9  Voltage and Current Monitoring in Buck
        1. 8.2.9.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.9.1.1 Input Overvoltage (ACOV)
          2. 8.2.9.1.2 System Overvoltage Protection (SYSOVP)
      10. 8.2.10 Battery Protection
        1. 8.2.10.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.10.2 Battery Over-Discharge Protection
      11. 8.2.11 Serial Interface
        1. 8.2.11.1 Data Validity
        2. 8.2.11.2 START and STOP Conditions
        3. 8.2.11.3 Byte Format
        4. 8.2.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.11.5 Slave Address and Data Direction Bit
        6. 8.2.11.6 Single Read and Write
        7. 8.2.11.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Map
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG11
      18. 8.4.18 REG12
      19. 8.4.19 REG13
      20. 8.4.20 REG14
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX VALUE
Voltage range (with respect to GND) VBUS (converter not switching) –2 22 V
PMID (converter not switching) –0.3 22 V
STAT –0.3 20 V
PG –0.3 7 V
PSEL –0.3 7 V
BTST –0.3 20 V
SW –3 16 V
BAT, SYS (converter not switching) –0.3 6 V
SDA, SCL, INT, REGN, CE –0.3 7 V
BTST TO SW –0.3 7 V
PGND to GND –0.3 0.3 V
BATSEN –0.3 7 V
Output sink current INT, STAT 6 mA
PG 6 mA
Junction temperature –40 150 °C
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VIN Input voltage 3.9 14(1) V
IIN Input current (VBUS) 3.25 A
ISYS Output current (SW) 3 A
VBAT Battery voltage 4.608 V
IBAT Fast charging current 3 A
Discharging current with internal MOSFET Up to 6 (continuos) A
9 (peak)
(Up to 1 sec duration)		 A
TA Operating free-air temperature range –40 85 °C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise.

7.4 Thermal Information

THERMAL METRIC(1) bq25898C UNIT
YFF (DSBGA)
42-BALL
RθJA Junction-to-ambient thermal resistance 53.5 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.2 °C/W
RθJB Junction-to-board thermal resistance 8.2 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 8.2 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IBAT Battery discharge current (BAT, SW, SYS) in buck mode VBAT = 4.2 V, V(VBUS) < V(UVLO), leakage between BAT and VBUS 5 µA
High-Z Mode, No VBUS, BATFET Disabled (REG09[5] = 1), Battery Monitor Disabled, TJ < 85°C 12 23 µA
High-Z Mode, No VBUS, BATFET Enabled (REG09[5] = 0), Battery Monitor Disabled, TJ < 85°C 32 60 µA
I(VBUS_HIZ) Input supply current (VBUS) in buck mode when High-Z mode is enabled V(VBUS)= 5 V, High-Z Mode, No Battery, Battery Monitor Disabled 15 35 µA
V(VBUS)= 12 V, High-Z Mode, No Battery, Battery Monitor Disabled 25 50 µA
I(VBUS) Input supply current (VBUS) in buck mode VBUS > V(UVLO), VBUS > VBAT, Converter not switching 1.5 3 mA
VBUS > V(UVLO), VBUS > VBAT, Converter switching, VBAT = 3.2V, ISYS = 0A 3 mA
VBUS > V(UVLO), VBUS > VBAT, Converter switching, VBAT = 3.8 V, ISYS = 0 A 3 mA
VBUS/BAT POWER UP
V(VBUS_OP) VBUS operating range 3.9 14 V
V(VBUS_UVLOZ) VBUS for active I2C, no battery 3.6 V
V(SLEEP) Sleep mode falling threshold 25 65 120 mV
V(SLEEPZ) Sleep mode rising threshold 130 250 370 mV
V(ACOV) VBUS over-voltage rising threshold 13.9 14.6 V
VBUS over-voltage falling threshold 13.3 13.9 V
tACOV_RISING ACOV rising deglitch VVBUS rising 1 µs
tACOV_FALLING ACOV falling deglitch VVBUS falling 1 ms
VBAT(UVLOZ) Battery for active I2C, no VBUS 2.3 V
VBAT(DPL) Battery depletion falling threshold 2.15 2.5 V
VBAT(DPLZ) Battery depletion rising threshold 2.35 2.7 V
V(VBUSMIN) Bad adapter detection threshold 3.8 V
I(BADSRC) Bad adapter detection current source 30 mA
POWER-PATH MANAGEMENT
VSYS Typical system regulation voltage I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled (REG09[5]=1) VBAT+
50 mV		 V
Isys = 0 A, VBAT< VSYS(MIN), BATFET Disabled (REG09[5]=1) VSYS(MIN) +
250 mV		 V
VSYS(MIN) Minimum DC system voltage output VBAT< VSYS(MIN), SYS_MIN = 3.5 V (REG03[3:1] = 101), ISYS= 0 A 3.60 3.75 V
VSYS(MAX) Maximum DC system voltage output VBAT = 4.35 V, SYS_MIN = 3.5 V (REG03[3:1] = 101), ISYS= 0 A 4.40 4.42 V
RON(RBFET) Top reverse blocking MOSFET(RBFET) on-resistance between VBUS and PMID TJ = -40°C - 85°C 28 40 mΩ
TJ = -40°C - 125°C 28 47 mΩ
RON(HSFET) Top switching MOSFET (HSFET) on-resistance between PMID and SW TJ = -40°C - 85°C 24 33 mΩ
TJ = -40°C - 125°C 24 40 mΩ
RON(LSFET) Bottom switching MOSFET (LSFET) on-resistance between SW and GND TJ = -40°C - 85°C 12 18 mΩ
TJ = -40°C - 125°C 12 21 mΩ
V(FWD) BATFET forward voltage in supplement mode BAT discharge current 10 mA 30 mV
BATTERY CHARGER
VBAT(REG_RANGE) Typical charge voltage range 3.840 4.608 V
VBAT(REG_STEP) Typical charge voltage step 16 mV
VBAT(REG) Charge voltage resolution accuracy VBAT = 4.208 V (REG06[7:2] = 010111) or
VBAT = 4.352 V (REG06[7:2] = 100000)
TJ = -40°C - 85°C		 -0.5% 0.5%
I(CHG_REG_RANGE) Typical fast charge current regulation range 0 3008 mA
I(CHG_REG_STEP) Typical fast charge current regulation step 64 mA
I(CHG_REG_ACC) Fast charge current regulation accuracy VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = -40°C - 85°C		 -20% 20%
VBAT= 3.1 V or 3.8 V, ICHG = 1792 mA
TJ = -40°C - 85°C		 -5% 5%
VBAT(LOWV) Battery LOWV falling threshold Fast charge to precharge, BATLOWV (REG06[1]) = 1 2.6 2.8 2.9 V
Battery LOWV rising threshold Precharge to fast charge, BATLOWV (REG06[1]) = 1
(Typical 200-mV hysteresis)		 2.8 3.0 3.15 V
Battery LOWV falling threshold Fast charge to precharge, BATLOWV (REG06[1]) = 0 2.5 2.6 2.7 V
Battery LOWV rising threshold Precharge to fast charge, BATLOWV (REG06[1]) = 0
(Typical 200-mV hysteresis)		 2.7 2.8 2.9 V
I(PRECHG_RANGE) Precharge current range 64 1024 mA
I(PRECHG_STEP) Typical precharge current step 64 mA
I(PRECHG_ACC) Precharge current accuracy VBAT = 2.6 V, IPRECHG = 256 mA –20% 20%
I(TERM_RANGE) Termination current range 64 1024 mA
I(TERM_STEP) Typical termination current step 64 mA
I(TERM_ACC) Termination current accuracy ITERM = 256 mA, ICHG≤ 1344 mA
TJ = -20°C - 85°C		 -20% 20%
ITERM = 256 mA, ICHG> 1344 mA
TJ = -20°C - 85°C		 -20% 20%
V(SHORT) Battery short voltage VBAT falling 2.0 V
V(SHORT_HYST) Battery short voltage hysteresis VBAT rising 200 mV
I(SHORT) Battery short current VBAT < 2.2 V 110 mA
V(RECHG) Recharge threshold below VBATREG VBAT falling, VRECHG (REG06[0] = 0) = 0 100 mV
VBAT falling, VRECHG (REG06[0] = 0) = 1 200 mV
RON(BATFET) SYS-BAT MOSFET (BATFET) on-resistance TJ = 25°C 5 7 mΩ
TJ = -40°C - 125°C 5 10 mΩ
RBATSEN BATSEN input resistance 800 kΩ
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE) Typical input voltage regulation range 3.9 15.3 V
VIN(DPM_STEP) Typical input voltage regulation step 100 mV
VIN(DPM_ACC) Input voltage regulation accuracy VINDPM = 4.4 V, 7.8 V, 10.8 V -3% 3%
IIN(DPM_RANGE) Typical input current regulation range 100 3250 mA
IIN(DPM_STEP) Typical input current regulation step 50 mA
IIN(DPM100_ACC) Input current 100mA regulation accuracy
VBAT = 5V, current pulled from SW		 IINLIM (REG00[5:0]) = 100 mA 85 90 100 mA
IIN(DPM_ACC) Input current regulation accuracy
VBAT = 5V, current pulled from SW		 USB150, IINLIM (REG00[5:0]) = 150 mA 125 135 150 mA
USB500, IINLIM (REG00[5:0]) = 500 mA 440 470 500 mA
USB900, IINLIM (REG00[5:0]) = 900 mA 750 825 900 mA
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA 1300 1400 1500 mA
IIN(START) Input current regulation during system start up VSYS = 2.2 V, IINLIM (REG00[5:0]) ≥ 200 mA 200 mA
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP) Battery over-voltage threshold VBAT rising, as percentage of VBAT(REG) 104%
VBAT(OVP_HYST) Battery over-voltage hysteresis VBAT falling, as percentage of VBAT(REG) 2%
IBAT(FET_OCP) System over-current threshold 9 A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy REG08[1:0] = 11 120 °C
TSHUT Thermal shutdown rising temperature Temperature rising 160 °C
TSHUT(HYS) Thermal shutdown hysteresis Temperature falling 30 °C
PWM
FSW PWM switching frequency, and digital clock Oscillator frequency 1.32 1.68 MHz
DMAX Maximum PWM duty cycle 97%
REGN LDO
V(REGN) REGN LDO output voltage V(VBUS) = 9 V, I(REGN) = 40 mA 5.6 6 6.4 V
V(VBUS) = 5 V, I(REGN) = 20 mA 4.7 4.8 V
I(REGN) REGN LDO current limit V(VBUS) = 9 V, V(REGN) = 3.8 V 50 mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES Resolution Rising threshold 7 bits
VBAT(RANGE) Typical battery voltage range V(VBUS) > VBAT + V(SLEEP) 2.304 4.848 V
V(VBUS) < VBAT + V(SLEEP) VSYS_MIN 4.848 V
V(BAT_RES) Typical battery voltage resolution 20 mV
V(SYS_RANGE) Typical system voltage range V(VBUS) > VBAT + V(SLEEP) 2.304 4.848 V
V(VBUS) < VBAT + V(SLEEP) VSYS_MIN 4.848 V
V(SYS_RES) Typical system voltage resolution 20 mV
V(VBUS_RANGE) Typical VVBUS voltage range V(VBUS) > VBAT + V(SLEEP) 2.6 15.3 V
V(VBUS_RES) Typical VVBUS voltage resolution 100 mV
IBAT(RANGE) Typical battery charge current range V(VBUS) > VBAT + V(SLEEP) and VBAT > VBAT(SHORT) 0 3.008 A
IBAT(RES) Typical battery charge current resolution 50 mA
LOGIC I/O PIN (CE, PSEL)
VIH Input high threshold level 1.3 V
VIL Input low threshold level 0.4 V
IIN(BIAS) High level leakage current Pull-up rail 1.8 V 1 µA
LOGIC I/O PIN (INT, STAT, PG)
VOL Output low threshold level Sink Current = 5 mA, Sink current 0.4 V
IOUT_BIAS High level leakage current Pull-up rail 1.8 V 1 µA
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SCL and SDA Pull-up rail 1.8 V 1.3 V
VIL Input low threshold level Pull-up rail 1.8 V 0.4 V
VOL Output low threshold level Sink Current = 5 mA, Sink current 0.4 V
IBIAS High level leakage current Pull-up rail 1.8 V 1 µA

7.6 Timing Requirements

MIN NOM MAX UNIT
VBUS/BAT POWER UP
tBADSRC Bad adapter detection duration 30 msec
BAT OVER-VOLTAGE PROTECTION
tBATOVP Battery over-voltage deglitch time to disable charge 1 µs
BATTERY CHARGER
tRECHG Recharge deglitch time 20 msec
BATTERY MONITOR
tCONV Conversion time CONV_RATE(REG02[6]) = 0 8 1000 msec
I2C INTERFACE
fSCL SCL clock frequency 400 KHz
DIGITAL CLOCK and WATCHDOG TIMER
fLPDIG Digital low power clock REGN LDO disabled 18 30 45 KHz
fDIG Digital clock REGN LDO enabled 1320 1500 1680 KHz
tWDT Watchdog reset time WATCHDOG (REG07[5:4])=11, REGN LDO disabled 100 160 sec
WATCHDOG (REG07[5:4])=11, REGN LDO enabled 136 160 sec

7.7 Typical Characteristics

bq25898C D001_slusch6.gif
VBAT = 3.8 V DCR = 10 mΩ
Figure 1. Charge Efficiency vs Charge Current
bq25898C D004_slusch6.gif
VBUS = 5 V
Figure 3. Charge Current Accuracy vs Charge Current I2C Setting
bq25898C D006_slusca6.gif
VBAT = 4.2 V
Figure 5. SYS Voltage Regulation vs System Load Current
bq25898C D008_slusca6.gif
Figure 7. Input Current Limit vs Temperature
bq25898C D002_slusca6.gif
Figure 2. System Light Load Efficiency vs System Light Load Current
bq25898C D005_slusca6.gif
VBAT = 2.6 V VBUS = 5 V SYSMIN = 3.5 V
Figure 4. SYS Voltage Regulation vs System Load Current
bq25898C D007_slusca6.gif
VBUS = 5 V
Figure 6. BAT Voltage vs Temperature
bq25898C D010_slusca6.gif
Figure 8. Charge Voltage Accuracy