JAJSPF6A December   2022  – October 2023 BQ27427

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Supply Current
    6. 5.6  Digital Input and Output DC Characteristics
    7. 5.7  LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics
    8. 5.8  LDO Regulator, Wake-up, and Auto-Shutdown AC Characteristics
    9. 5.9  ADC (Temperature and Cell Measurement) Characteristics
    10. 5.10 Integrating ADC (Coulomb Counter) Characteristics
    11. 5.11 Integrated Sense Resistor Characteristics, –40°C to 85 °C
    12. 5.12 I2C-Compatible Interface Communication Timing Characteristics
    13. 5.13 SHUTDOWN and WAKE-UP Timing
    14. 5.14 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Communications
        1. 6.3.1.1 I2C Interface
        2. 6.3.1.2 I2C Time Out
        3. 6.3.1.3 I2C Command Waiting Time
        4. 6.3.1.4 I2C Clock Stretching
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 BAT Voltage Sense Input
        2. 7.2.2.2 Integrated LDO Capacitor
      3. 7.2.3 External Thermistor Support
      4. 7.2.4 Application Curves
  9. 8 Power Supply Recommendation
    1. 8.1 Power Supply Decoupling
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Related Documentation
    2. 10.2 Trademarks
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.12 I2C-Compatible Interface Communication Timing Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
MINNOMMAXUNIT
Standard Mode (100 kHz)
td(STA)Start to first falling edge of SCL4μs
tw(L)SCL pulse duration (low)4.7μs
tw(H)SCL pulse duration (high)4μs
tsu(STA)Setup for repeated start4.7μs
tsu(DAT)Data setup timeHost drives SDA250ns
th(DAT)Data hold timeHost drives SDA0ns
tsu(STOP)Setup time for stop4μs
t(BUF)Bus free time between stop and startIncludes Command Waiting Time66μs
tfSCL or SDA fall time(1)300ns
trSCL or SDA rise time(1)300ns
fSCLClock frequency(2)100kHz
Fast Mode (400 kHz)
td(STA)Start to first falling edge of SCL600ns
tw(L)SCL pulse duration (low)1300ns
tw(H)SCL pulse duration (high)600ns
tsu(STA)Setup for repeated start600ns
tsu(DAT)Data setup timeHost drives SDA100ns
th(DAT)Data hold timeHost drives SDA0ns
tsu(STOP)Setup time for stop600ns
t(BUF)Bus free time between stop and startIncludes Command Waiting Time66μs
tfSCL or SDA fall time(1)300ns
trSCL or SDA rise time(1)300ns
fSCLClock frequency(2)400kHz
(1) Specified by design. Not production tested.
(2) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See Section 6.3.1.1 and Section 6.3.1.3.)
GUID-0E9648D3-67EC-405B-A28E-A03CB8550DAE-low.gifFigure 5-1 I2C-Compatible Interface Timing Diagrams